We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 51282

LogiCORE IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) v2.4 - Updates needed to reset/initialization logic for cable pull/ RX data input not present


If targeting 7 series FPGAs with the Ten Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) v2.4 core, updates are needed to the reset/initialization logic for the core and GT, if the core will be operating in a system where there could be a cable unplug, a link partner reset, or other cause for no RX data to be present at the serial input to the GT. Failures include not establishing a link or FCS errors at the MAC level.


The attached rev2 update resolves:
- Issues seen in hardware on cable unplug or reset resulting in failure to establish a link or FCS errors at the MAC level
- BASE-KR Training not completing after reset (Xilinx Answer 51312)

Include in the rev2 update are the previous rev1 updates:
- Improved hot-plug capabilities
- Separation of the tx and rx resets in the example design and block level
- Updates to improve timing closure in Vivado (Xilinx Answer 50809)
- Connection of signal_detect port to core FSMs

The v2.4 rev2 core is preproduction and hardware testing continues.

To install the patch, follow the instructions in the included readme file.

AR# 51282
Date Created 08/13/2012
Last Updated 08/21/2012
Status Active
Type General Article
  • 10 Gigabit Ethernet PCS-PMA with FEC/Auto-Negotiation for backplanes (10GBASE-KR)
  • Ten Gigabit Ethernet PCS/PMA