The MIG 7 Series GUI includes multiple flows for creating memory interface pin-outs as well as verifying changes to previously generated pin-outs. The 7 series FPGA banks are comprised of four T* byte groups. Each byte group is made up of 12 I/O. The general MIG 7 Series design creation flow ("New Design") allows users to select which data or address/control/command groups are assigned to which FPGA bank byte groups. The "Fixed Pin-Out" design generation flow allows users to manually select each pin or upload a UCF. The tool will then verify the pins selected, report any warnings/errors, and upon zero reported errors, generates the appropirate MIG 7 Series design.
When pin changes are made to the generated MIG 7 Series UCF, the Verify Pin Changes and Update Design flow can be used to upload the modified UCF and generate a design with the appropriate UCF and rtl parameter settings.
Manually changing or creating a pin-out without using the MIG 7 Series tool for verification is not supported and can lead to unroutable designs or failures in hardware.
Additional Information/Commonly Asked Questions:(Xilinx Answer 41752) MIG 7 Series DDR3/DDR2 - Can a x16 interface fit into a single bank?
(Xilinx Answer 41706) MIG 7 Series - Can FPGA banks be shared amongst memory interfaces?
(Xilinx Answer 46082) MIG 7 Series DDR3 - How to enable Dynamic ODT special use case to remove need to have an ODT pin on the FPGA
(Xilinx Answer 40603) MIG 7 Series FPGAs DDR3/DDR2 - Clocking Guidelines
(Xilinx Answer 42036) MIG 7 Series - Internal/External VREF Guidelines