Version Found: MIG 7 Series v1.5

The MIG 7 Series DDR3/DDR2 design includes an ECC Self-Test Functionality controlled by a top-level RTL parameter "ECC_TEST." 

By default, MIG sets this parameter to "OFF," which means that the ECC part of the data written to the DRAM array is not visible at the user interface.

This can be problematic for system self-test because there is no way to test the bits in the DRAM array corresponding to the ECC bits.

There is also no way to send errors to test the ECC generation and correction logic. 

By setting ECC_TEST to "ON," a DRAM array test mode can be generated.

When the ECC_TEST parameter is "ON," the entire width of the DQ data bus is extended through the read and write buffers in the user interface.

Also, the ECC correct enable is deasserted. 

 

However after manually modifying the MIG design to set ECC_TEST to "ON," the design fails during synthesis with an error similar to the following:
 

This error occurs because of an rtl issue where wr_data_mask is not declared with the appropriate width. 

To work around this issue, manually change the width of wr_data_mask:

From:
 

To: