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AR# 51369

Design Advisory for the Artix-7 FPGA GTP Transceiver - Attribute Updates, Issues, and Work-arounds for Initial/General Engineering Sample (ES) Silicon


This answer record contains information on attribute settings, issues, and work-arounds for the Artix-7 FPGA GTP Transceiver Initial/General Engineering Sample (ES) Silicon


1. GTP Transceiver Attribute Updates for Initial/General Engineering Sample (ES) Silicon

This table shows the GTP attribute updates required for reliable operation of the Initial/General ES silicon. When using v2.4 or earlier of the 7 Series FPGAs Transceivers Wizard, some of these attribute updates may need to be made manually to the GTP wrapper generated by the wizard. When using v2.5 of the wizard in ISE 14.5, the attributes are generated natively (except RX_OS_CFG and RXLPM_OSINT_CFG) by the wizard. When using v2.5 of the wizard in Vivado 2013.1, the exceptions are BIAS_CFG, PMA_RSV2, RXCDR_CFG, RX_OS_CFG and RXLPM_OSINT_CFG and these need to be set manually in the wrapper generated by the wizard. The updated RX reset sequence covered in (Xilinx Answer 53561) and the TX sync controller change covered in (Xilinx Answer 55009) are included in v2.5 of the wizard.


PLL0_CFG 27'h01F03DC(1)
PLL1_CFG 27'h01F03DC(1)
BIAS_CFG 64'h0000000000050001
RX_CM_TRIM 4'b1010(3)
RXCDR_LOCK_CFG(4) 6'b001001
RX_DEBUG_CFG 14'h000
RXPI_CFG0 3'b000
RXPI_CFG1 1'b1
RXPI_CFG2 1'b1
RX_BIAS_CFG 16'h0F33
RXLPM_CFG 4'b0110
RXLPM_GC_CFG2 3'b001
RXLPM_HF_CFG2 5'b01010
RXLPM_LF_CFG2 5'b01010
RXLPM_GC_CFG 9'b111100010
CFOK_CFG 42'h490_0004_0E80
CFOK_CFG2 7'b0100000
CFOK_CFG3 7'b0100000
RXOSINTCFG (port) 4'b0010
RXOSINTEN  (port) 1
PMA_RSV2 32h'00002040
RX_OS_CFG 13'h0080

RXCDR_CFG(5) Full-rate: RXOUT_DIV=1 (Line rate 3.2 to 6.6 Gb/s) Half-rate: RXOUT_DIV=2 (Line rate 1.6 to 3.3 Gb/s) Quarter-rate: RXOUT_DIV=4 (Line rate 0.8 to 1.65 Gb/s) One-eighth rate: RXOUT_DIV=8 (Line rate 0.5 to 0.825Gb/s)
Scrambled and 8B/10B with Pre-scrambling patterns CDR setting: < +/- 200 ppm, +/- 700 ppm, +/- 1250 ppm


CDR setting: < +/- 200 ppm, +/- 700 ppm, +/- 1250 ppm

CDR setting: < +/- 200 ppm, +/- 700 ppm, +/- 1250 ppm


CDR setting: < +/- 200 ppm, +/- 700 ppm, +/- 1250 ppm


8B/10B without Pre-scramble pattern CDR setting < +/- 200 ppm


CDR setting < +/- 700 ppm, +/- 1250 ppm


CDR setting < +/- 200 ppm


CDR setting < +/- 700 ppm, +/- 1250 ppm


CDR setting < +/- 200 ppm

CDR setting < +/- 700 ppm, +/- 1250 ppm

CDR setting < +/- 200 ppm

CDR setting < +/- 700 ppm, +/- 1250 ppm

SATA REFCLK PPM with SSC setting(6) 83'h0_0000_87FE_2060_2444_1010 (SATA Gen3) 83'h0_0000_47FE_2060_2448_1010 (SATA Gen2) 83'h0_0000_47FE_1060_2448_1010 (SATA Gen1)



  1. Should be set to 27'h01F024C for PCI-Express Gen 1 and Gen 2.
  2. For RXLPM_INCM_CFG and RXLPM_IPCM_CFG settings, refer to the RX termination use modes section below.
  3. Programmable, set to 800 mV. Applies when RX_CM_SEL = 2'b11.
  4. The port RXCDRLOCK is not supported. It is recommended to verify the incoming data.
  5. The RXCDR_CFG settings are preliminary and under characterization. The updated settings will be added when available.
  6. This setting is to support SATA requirement for REFCLK PPM with SSC: +/- 700PPM with 33KHz FM Triangular modulation of -5000PPM.

2. Use Modes/Issues

2.1. RX Termination Use Modes

For the different GTP RX termination use modes, see (Xilinx Answer 51448).

2.2. Buffer Bypass Mode

For the latest buffer bypass attributes, see (Xilinx Answer 47492).

2.3. OOB Use Mode

OOB circuitry is only used for applications such as PCI Express, SATA/SAS, etc. For designs not using OOB, PCS_RSVD_ATTR[8] is set to 1'b0; RXELECIDLEMODE[1:0] must be set to 2'b11 and RXBUF_RESET_ON_EIDLE must be set to FALSE.

2.4. RX Reset Sequence

For the RX reset sequence requirement for Production Silicon, please refer to (Xilinx Answer 53561). This updated sequence is required for production silicon but can also be used on ES silicon. When using v2.5 of the 7 Series FPGAs Transceivers Wizard, this reset sequence is included automatically.  


Clock Forwarding Use Mode:

This GTPE2_COMMON/BIAS_CFG use mode requirement applies to any existing design when the criteria below are met or in general to any new designs with the Artix-7 GTP transceivers. Following this use mode will ensure that the correct BIAS_CFG setting gets propagated which will result in improved TX jitter performance.
  • The reference clock is forwarded from one Quad (essentially just the IBUFDS_GTE2 is used and this Quad is not being used otherwise in the design) to another Quad
  • GTP transceiver running at -2 and -3 line rates
  • Voltage swing of the reference clock is less than 400 mV (differential peak-to-peak)
The GTPE2_COMMON module in the reference clock source Quad where IBUFDS_GTE2 is located should be instantiated and the BIAS_CFG value mentioned in the attributes table should be used in the wrapper or UCF. This use mode is not implemented automatically when using v2.5 of the 7 Series FPGAs Transceivers Wizard. 
2.6. TX Sync Controller Change
Please refer to (Xilinx Answer 55009) for details about TX sync controller change for phase alignment in buffer bypass mode. This is fixed in v2.5 of the 7 Series FPGAs Transceivers Wizard.
Revision History
03/27/2014 - Updated RXCDR_CFG setting for SATA
05/09/2013 - Added information about the GT Wizard v2.5 in ISE 14.5/Vivado 2013.1 and updated the RXLPM_OSINT_CFG value.
04/12/2013 - Added RX_OS_CFG value to the table, added the RX reset sequence, GTPE2_COMMON/BIAS_CFG use mode when clock forwarding and TX sync controller change sections.
01/18/2013 - Added RXCDR_CFG settings for one-eighth rate and SATA SSC. Re-arranged the RXCDR_CFG table to make it easy to read. Added PMA_RSV2 to the table.
12/19/2012 - Updated the BIAS_CFG setting and added the OOB use mode
11/01/2012 - Updated to include General ES silicon
09/27/2012 - Updated RXCDR_CFG and RXLPM_OSINT_CFG. Added buffer bypass mode to the use modes section
09/18/2012 - Updated PLL0/1_CFG and RXCDR_CFG values and added some attributes to the attributes table
08/23/2012 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51456 Design Advisory Master Answer Record for Artix-7 FPGA N/A N/A
47852 7 Series FPGAs GTP Transceivers - Known Issues and Answer Record List N/A N/A
AR# 51369
Date Created 08/23/2012
Last Updated 04/17/2014
Status Active
Type Design Advisory
  • Artix-7