1. GTP Transceiver Attribute Updates for Initial/General Engineering Sample (ES) Silicon
This table shows the GTP attribute updates required for reliable operation of the Initial/General ES silicon. These attribute updates must be made manually to the GTP wrapper generated by the 7 series FPGA Transceiver Wizard version 2.2 in ISE 14.2/Vivado 2012.2 design tools. These are generated natively by version 2.3 or later of the wizard in the ISE 14.3/Vivado 2012.3 or later release, except for BIAS_CFG and RXCDR_CFG under certain scenarios that need to be set manually.
| Attribute |
Value |
| PLL0_CFG | 27'h01F03DC(1) |
| PLL1_CFG | 27'h01F03DC(1) |
| BIAS_CFG | 64'h0000000000050001 |
| RXLPM_INCM_CFG | 1'b1(2) |
| RXLPM_IPCM_CFG | 1'b0(2) |
| RX_CM_TRIM | 4'b1010(3) |
| RXCDR_LOCK_CFG(4) | 6'b001001 |
| RX_DEBUG_CFG | 14'h000 |
| RXPI_CFG0 | 3'b000 |
| RXPI_CFG1 | 1'b1 |
| RXPI_CFG2 | 1'b1 |
| RX_BIAS_CFG | 16'h0F33 |
| RXLPM_CFG | 4'b0110 |
| RXLPM_GC_CFG2 | 3'b001 |
| RXLPM_HF_CFG2 | 5'b01010 |
| RXLPM_LF_CFG2 | 5'b01010 |
| RXLPM_GC_CFG | 9'b111100010 |
| RXLPM_OSINT_CFG | 3'b000 |
| CFOK_CFG | 42'h490_0004_0E80 |
| CFOK_CFG2 | 7'b0100000 |
| CFOK_CFG3 | 7'b0100000 |
| RXOSCALRESET_TIMEOUT | 5'b00000 |
| RXOSINTCFG (port) | 4'b0010 |
| RXOSINTEN (port) | 1 |
| PMA_RSV2 | 32h'00002040 |
| RXCDR_CFG(5) | Full-rate: RXOUT_DIV=1 (Line rate 3.2 to 6.6 Gb/s) | Half-rate: RXOUT_DIV=2 (Line rate 1.6 to 3.3 Gb/s) | Quarter-rate: RXOUT_DIV=4(Line rate 0.8 to 1.65 Gb/s) | One-eighth rate: RXOUT_DIV=8(Line rate 0.5 to 0.825Gb/s) |
| Scrambled and8B/10B with Pre-scrambling patterns | CDR setting: < +/- 200 ppm,+/- 700 ppm,+/- 1250 ppm 83'h0_0011_07FE_2060_2104_1010 |
CDR setting: < +/- 200 ppm,+/- 700 ppm,+/- 1250 ppm |
CDR setting: < +/- 200 ppm,+/- 700 ppm,+/- 1250 ppm 83'h0_0011_07FE_0860_2110_1010 |
CDR setting: < +/- 200 ppm,+/- 700 ppm,+/- 1250 ppm 83'h0_0011_07FE_0860_2110_1010 |
| 8B/10B without Pre-scramble pattern | CDR setting < +/- 200 ppm 83'h0_0001_07FE_4060_0104_1010 |
CDR setting < +/- 200 ppm 83'h0_0001_07FE_2060_0104_1010 |
CDR setting < +/- 200 ppm 83'h0_0001_07FE_1060_0104_1010 CDR setting < +/- 700 ppm, +/- 1250 ppm |
CDR setting < +/- 200 ppm 83'h0_0001_07FE_0860_0104_1010 CDR setting < +/- 700 ppm, +/- 1250 ppm |
| SATA REFCLK PPM with SSC setting(6) | 83'h0_0000_87FE_2060_2448_1010 | 83'h0_0000_47FE_2060_2450_1010 | 83'h0_0000_47FE_1060_2450_1010 |
Notes:
2. Use Modes
2.1. RX Termination Use Modes
For the different GTP RX termination use modes,see (Xilinx Answer 51448).
2.2 Buffer Bypass Mode
For the latest buffer bypass attributes, see (Xilinx Answer 47492).
2.3 OOB Use Mode
OOB circuitry is only usedfor applications such as PCI Express, SATA/SAS, etc. For designs not using OOB, PCS_RSVD_ATTR[8] is set to 1'b0; RXELECIDLEMODE[1:0] must be set to 2'b11and RXBUF_RESET_ON_EIDLE must be set to FALSE.
Revision History
01/18/2013 - Added RXCDR_CFG settings for one-eighth rate and SATA SSC. Re-arranged the RXCDR_CFG table to make it easy to read. Added PMA_RSV2 to the table.
12/19/2012 - Updated the BIAS_CFG setting and added the OOB use mode
11/01/2012 - Updated to include General ES silicon
09/27/2012 - Updated RXCDR_CFG and RXLPM_OSINT_CFG. Added buffer bypass mode to the use modes section
09/18/2012 - Updated PLL0/1_CFG and RXCDR_CFG values and added some attributes to the attributes table
08/23/2012 - Initial release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 51456 | Design Advisory Master Answer Record for Artix-7 FPGA | N/A | N/A |