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AR# 51402 7 Series Integrated Block for PCI Express v1.6 - Incorrect RX_CM_TRIM setting for Artix-7 FPGAs

Description

This article describes an incorrect Artix-7 GTP Transceiver setting by the PCIe core v1.6 or earlier thatmay causePCI Express link training problems.

Solution

The PCI Express core v1.6 or earliersets the RX_CM_TRIM[3:0] attribute incorrectly to 3'b010 (250 mV common mode). This should be updated to the correct setting of 4'b1010 (800 mV common mode) when RX_CM_SEL[1:0] = 2'b11 (programmable).

This will be fixed in a future version of the PCI Express core.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47852 7 Series FPGAs GTP Transceivers - Known Issues and Answer Record List N/A N/A

Actions

AR# 51402
Date Created 08/23/2012
Last Updated 08/27/2012
Status Active
Type General Article
Devices
  • Artix-7
IP
  • 7 Series Integrated Block for PCI Express (PCIe)
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