Design Advisory Alerted on April 3, 2013
(Xilinx Answer 55009) Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode

Design Advisory Alerted on February 4, 2013
(Xilinx Answer 53561) Design Advisory for Artix-7 FPGA GTP Transceiver - RX Reset Sequence Requirement for Production Silicon

Design Advisory Alerted on January 21, 2013
(Xilinx Answer 51369) Updated Design Advisory for the Artix-7 FPGA GTP Engineering Sample (ES) Silicon with RXCDR_CFG settings for one-eighth rate, SATA SSC and added PMA_RSV2 to the table

Design Advisory Alerted on December 24, 2012
(Xilinx Answer 51369) Updated Design Advisory for the Artix-7 FPGA GTP Engineering Sample (ES) Silicon with the latest BIAS_CFG setting and added the OOB use mode

Design Advisory Alerted on November 5, 2012
(Xilinx Answer 51369) Updated Design Advisory for the Artix-7 FPGA GTP Transceiver to include General Engineering Sample (ES) Silicon

Design Advisory Alerted on October 29, 2012
(Xilinx Answer 52193) Design Advisory for 7 Series BPI Multiboot - When fallback occurs flash access is always in BPI asynchronous Mode

Design Advisory Alerted on October 1, 2012
(Xilinx Answer 51369) - Updated Design Advisory for the Artix-7 FPGA GTP Transceiver Initial Engineering Sample (ES) Silicon with the latest GTP attribute values and added buffer bypass use mode

Design Advisory Alerted on September 24, 2012
(Xilinx Answer 51369) - Updated Design Advisory for the Artix-7 FPGA GTP Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon with the latest GTP attribute values

Design Advisory Alerted on September 10, 2012
(Xilinx Answer 51580) - Design Advisory for 14.1/14.2 Timing Analysis 7 Series FPGAs - Clock Arrival Times are Incorrect for Block RAM (BRAM) or FIFO Components for PERIOD constraint analysis

Design Advisories alerted on August 27, 2012
(Xilinx Answer 51369) - Design Advisory for the Artix-7 FPGA GTP Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon
(Xilinx Answer 51017) - Design Advisory for the Artix-7 GTP Transceiver Power-Up/Power-Down

Revision History
04/03/13 - Added 55009
01/31/13 - Added 53561
01/18/13 - Updated 51369
12/19/12 - Updated 51369
11/01/12 - Updated 51369
10/25/12 - Added 52193
09/28/12 - Updated 51369
09/18/12 - Updated 51369
09/10/12 - Added 51580
08/23/12 - Initial release