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AR# 51456

Design Advisory Master Answer Record for Artix-7 FPGA

Description

Design Advisories are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notifications System.

This Design Advisory covers Artix-7 devices and related issues that impact Artix-7 FPGA designs.

 

Solution

 

Design Advisories Alerted on April 18, 2016

 

(Xilinx Answer 66173) Design Advisory for Vivado 2015.4 - Vivado Timing WNS Alert - Missing Timing Arc on BUFR to BUFG clock path causes hold violations on board


Design Advisories Alerted on November 10, 2014

 
(Xilinx Answer 62631) Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 Series and UltraScale FPGAs

 

Design Advisories Alerted on June 16, 2014

(Xilinx Answer 59294) Design Advisory GT wizard - CPLL causes power spike on power up for 7 series Transceivers

Design Advisories Alerted on May 26, 2014

(Xilinx Answer 60356) Design Advisory for 7 Series FPGAs Transceivers Wizard v3.2 or earlier - Required XDC constraint Updates
(Xilinx Answer 60489) Design Advisory for 7 Series FPGAs Transceivers Wizard v3.2 or earlier: GTH/GTP Production RX reset sequence can get stuck

 

Design Advisory Alerted on April 21, 2014

(Xilinx Answer 51369) Updated Design Advisory for the Artix-7 FPGA GTP Transceiver with the RXCDR_CFG setting for SATA based on protocol characterization


Design Advisory Alerted on January 27, 2014

(Xilinx Answer 58162) Design Advisory for Artix-7 FPGA Wire-bond Package Devices - SelectIO prohibits pin list when GTP Transceivers are used


Design Advisory Alerted on September 16, 2013

(Xilinx Answer 57193) Design Advisory for Artix-7, Kintex-7, Virtex-7, Zynq-7000 Packaging - The 7 Series Thermal Resistance Values (Theta-JA, Theta-JB, and Theta-JC) are being updated with more accurate values, many of which are substantially changed

Design Advisory Alerted on August 26, 2013

(Xilinx Answer 57045) Design Advisory for Artix-7/Kintex-7 - When CFGBVS is set to VCCO of Bank 0, then Banks 14 and 15 are limited to 3.3V or 2.5V for Configuration

Design Advisory Alerted on August 19, 2013

(Xilinx Answer 55009) Updated Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode with links to answer records for IPs

Design Advisory Alerted on May 20, 2013

(Xilinx Answer 55009) Updated Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode with links to answer records for IPs

Design Advisories Alerted on May 13, 2013

(Xilinx Answer 55366) Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - Transceiver Wizard Sets Suboptimal RX Termination Use Modes
(Xilinx Answer 55791) Design Advisory for 7 Series FPGAs Transceivers Wizard - Required Updates to Wizard v2.5
(Xilinx Answer 51369) Updated Design Advisory for the Artix-7 FPGA GTP Engineering Sample (ES) Silicon with information about the GT wizard v2.5 in ISE 14.5/Vivado 2013.1 and updated the RXLPM_OSINT_CFG value.

 

Design Advisory Alerted on April 15, 2013

(Xilinx Answer 51369) Updated Design Advisory for the Artix-7 FPGA GTP Engineering Sample (ES) Silicon with RX_OS_CFG value and added the RX reset sequence, GTPE2_COMMON/BIAS_CFG use mode when clock forwarding and TX sync controller change sections

 

Design Advisory Alerted on April 3, 2013

(Xilinx Answer 55009) Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode

Design Advisory Alerted on February 4, 2013

(Xilinx Answer 53561) Design Advisory for Artix-7 FPGA GTP Transceiver - RX Reset Sequence Requirement for Production Silicon

Design Advisory Alerted on January 21, 2013

(Xilinx Answer 51369) Updated Design Advisory for the Artix-7 FPGA GTP Engineering Sample (ES) Silicon with RXCDR_CFG settings for one-eighth rate, SATA SSC and added PMA_RSV2 to the table

Design Advisory Alerted on December 24, 2012

(Xilinx Answer 51369) Updated Design Advisory for the Artix-7 FPGA GTP Engineering Sample (ES) Silicon with the latest BIAS_CFG setting and added the OOB use mode

Design Advisory Alerted on November 5, 2012

(Xilinx Answer 51369) Updated Design Advisory for the Artix-7 FPGA GTP Transceiver to include General Engineering Sample (ES) Silicon

Design Advisory Alerted on October 29, 2012

(Xilinx Answer 52193) Design Advisory for 7 Series BPI Multiboot - When fallback occurs flash access is always in BPI asynchronous Mode

Design Advisory Alerted on October 1, 2012

(Xilinx Answer 51369) Updated Design Advisory for the Artix-7 FPGA GTP Transceiver Initial Engineering Sample (ES) Silicon with the latest GTP attribute values and added buffer bypass use mode

Design Advisory Alerted on September 24, 2012

(Xilinx Answer 51369) Updated Design Advisory for the Artix-7 FPGA GTP Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon with the latest GTP attribute values

Design Advisory Alerted on September 10, 2012

(Xilinx Answer 51580) Design Advisory for 14.1/14.2 Timing Analysis 7 Series FPGAs - Clock Arrival Times are Incorrect for Block RAM (BRAM) or FIFO Components for PERIOD constraint analysis

Design Advisories alerted on August 27, 2012

(Xilinx Answer 51369) Design Advisory for the Artix-7 FPGA GTP Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon
(Xilinx Answer 51017) Design Advisory for the Artix-7 GTP Transceiver Power-Up/Power-Down

Revision History

05/26/14 Added 60356, 60489
04/04/14 Updated 51369
01/23/14 Added 58162
09/12/13 Added 57193
08/19/13 Added 57045
08/16/13 Updated 55009
05/16/13 Updated 55009
05/13/13 Added 55366 and 55791, updated 51369
04/12/13 Updated 51369
04/03/13 Added 55009
01/31/13 Added 53561
01/18/13 Updated 51369
12/19/12 Updated 51369
11/01/12 Updated 51369
10/25/12 Added 52193
09/28/12 Updated 51369
09/18/12 Updated 51369
09/10/12 Added 51580
08/23/12 Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
53980 Design Advisory Master Answer Record for Artix-7 FPGA AC701 Evaluation Kit N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
51369 Design Advisory for the Artix-7 FPGA GTP Transceiver - Attribute Updates, Issues, and Work-arounds for Initial/General Engineering Sample (ES) Silicon N/A N/A
51017 Design Advisory for the Artix-7 GTP Transceiver Power-Up/Power-Down N/A N/A
51580 Design Advisory for 14.1/14.2 Timing Analysis 7 Series - Clock Arrival Times are Incorrect for Block RAM (BRAM) or FIFO Components for PERIOD constraint analysis N/A N/A
52193 Design Advisory for 7 Series BPI Multiboot - When fallback occurs, flash access is always in BPI Asynchronous Mode N/A N/A
53561 Design Advisory for Artix-7 FPGA GTP Transceivers: RX Reset Sequence Requirement for Production Silicon N/A N/A
55791 Design Advisory for 7 Series FPGAs Transceivers Wizard - Required Updates to Wizard v2.5 N/A N/A
55366 Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers: Transceiver Wizard Sets Suboptimal RX Termination Use Modes N/A N/A
57045 Design Advisory for Artix-7, Kintex-7 - When CFGBVS is set to VCCO of Bank 0, then Banks 14 and 15 are limited to 3.3V or 2.5V for Configuration N/A N/A
57193 Design Advisory for Artix-7, Kintex-7, Virtex-7, Zynq-7000 Packaging - The 7 Series Thermal Resistance Values (Theta-JA, Theta-JB, and Theta-JC) are being updated with more accurate values, many of which are substantially changed N/A N/A
58162 Design Advisory for Artix-7 FPGA Wire-bond Package Devices - SelectIO prohibits pin list when GTP Transceivers are used N/A N/A
62631 Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 series and UltraScale FPGAs N/A N/A

Associated Answer Records

AR# 51456
Date Created 08/23/2012
Last Updated 04/18/2016
Status Active
Type Design Advisory
Devices
  • Artix-7