This section of the MIG 7 Series Design Assistant focuses on Board Layout and Design Guidelines for 7 Series DDR3/DDR2 designs. Please select from the below options to find information related to your specific question.
Note: This answer record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
The 7 Series DDR2/DDR3 Design requires specific board layout and design rules be followed in order for the design to behave correctly at the target memory data rate in hardware. The layout and design guidelines are documented in the DDR2 and DDR3 Memory Interface Solution > Design Guidelines section of the 7 Series FPGAs Memory Interface Solutions User Guide. It is important that these guidelines be followed.
A critical step in verifying board layout guidelines for memory interface designs includes using IBIS to run signal integrity simulations. Remember to run these simulations for both pre-board layout and post-board layout. These simulations confirm the signal integrity on the board.
The following Answer Records provide detailed information on the board layout requirements.
If after verifying that these rules have been followed, errors are seen in hardware, please refer back to the main Hardware section of this Design Assistant to look into Pin-out/Banking Requirements and Hardware Debug.