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AR# 51511

14.x Timing - How do I remove a path from HSIO GTPCLKOUT00 pin to IODELAY IOCLK0 pin from "Unconstrained path analysis"?


The following path is listed in the "Unconstrained path analysis". How do I constrain this path so that it is removed from the "Unconstrained path analysis"?

Delay: 11.005ns (data path)
Source: s6_pcie_v1_4_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i (HSIO)
Destination: mig_v3_6_inst/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/IODRP2_RZQ (OTHER)
Data Path Delay: 11.005ns (Levels of Logic = 5)

Maximum Data Path at Slow Process Corner: s6_pcie_v1_4_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i to mig_v3_6_inst/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/IODRP2_RZQ
Location Delay typeDelay(ns) Physical Resource
Logical Resource(s)
--------------------------------------------------------------------------------------------- -------------------
BUFIO2_X2Y28.I net (fanout=1)e 0.582s6_pcie_v1_4_i/gt_refclk_out<0>
BUFIO2_X2Y28.DIVCLK Tbufcko_DIVCLK 0.190s6_pcie_v1_4_i/gt_refclk_bufio2
PLL_ADV_X0Y2.CLKIN1 net (fanout=1) e 0.000 s6_pcie_v1_4_i/gt_refclk_buf
PLL_ADV_X0Y2.CLKOUT3Tpllcko_CLK 1.214s6_pcie_v1_4_i/pll_base_i/PLL_ADV
BUFGMUX_X2Y2.I0net (fanout=1) e 0.632 s6_pcie_v1_4_i/clk_100
PLL_ADV_X0Y1.CLKIN1net (fanout=1) e 1.893 clk_100
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK 1.214 mig_v3_6_inst/memc3_infrastructure_inst/u_pll_adv
BUFPLL_MCB_X0Y5.PLLIN0 net (fanout=1)e 1.283mig_v3_6_inst/memc3_infrastructure_inst/clk_2x_0
BUFPLL_MCB_X0Y5.IOCLK0Tbufcko_IOCLK0.390 mig_v3_6_inst/memc3_infrastructure_inst/BUFPLL_MCB1
IODELAY_X0Y5.IOCLK0net (fanout=34) e 3.398mig_v3_6_inst/c3_sysclk_2x
---------------------------------------------------------------------------------------------- ---------------------------
Total 11.005ns (3.217ns logic, 7.788ns route)
(29.2% logic, 70.8% route)


This is a clock path thatdoes not needto be constrained. Unfortunately, there is no way to constrain this path to remove it from the "Unconstrained path analysis".

  • FROM-TO TIG is not a good solution
    A TIG on the clock path corrupts the clock skew analysis for this clock, sousingFROM-TO TIG to constrain this path is not a good solution.
  • Normal FROM-TO constraint with a large requirement does not cover this clock path
    Since the destination pin is a clock pin, when using a normal FROM-TO constraint on this path, the Timing engine moves the requirement from the clock pin to the data pin of IODELAY component and the timing analysis only covers the data path. Therefore, the clock path is still unconstrained and is reported in the unconstrained path report.

AR# 51511
Date Created 11/12/2012
Last Updated 11/13/2012
Status Active
Type General Article
  • Spartan-6
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14