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AR# 51533

Design Assistant for Vivado Synthesis - Help with SystemVerilog Tasks and Functions Support


This answer record describes SystemVerilog tasks and functions supported by Vivado Synthesis and also provides coding examples for them. These coding examples are attached to this answer record. The answer record also contains information related to known issues and good coding practices.

Note: Each coding example can be used to directly create a Vivado project. Please refer to the header in each source file for the SystemVerilog constructs covered in each example.


SystemVerilog Tasks and Functions that are supported in Vivado Synthesis.

The following are the SystemVerilog Tasks and Functions structures that are supported in Vivado Synthesis. Please refer to Table 1-1 in this answer record for the related coding examples.

  1. SystemVerilog has static and automatic tasks and functions. Vivado synthesis treats all tasks and functions as automatic.
  2. For non-void functions, a value can be returned by assigning the function name to a value or by using return with a value. The return statement shall override any value assigned to the function name.


Coding example for Tasks and Functions

Table 1-1
Coding example name Data Types


  • automatic function and void function
  • task


Associated Attachments

Name File Size File Type
task_function_example.zip 2 KB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51360 Design Assistant for Vivado Synthesis - Help with SystemVerilog Support N/A N/A
AR# 51533
Date Created 08/29/2012
Last Updated 04/03/2013
Status Active
Type Solution Center
  • Vivado Design Suite