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AR# 51567

MIG 7 Series QDRII+ - How are CQ and CQ# used in the MIG QDRII+ core?


How are CQ and CQ# memory read clocksused in the MIG 7 Series QDRII+read data path?


In General, the CQ/CQ# memory read clocks can be used as a differential input but the MIG 7 Series QDRII+ design does not.MIG treats the CQ/CQ# as two single end input, whereCQ and CQ# will drive different components in different situations. Both CQ/CQ# are routed through a BUFMR and then,depending on the QDRII+ component read latency value,drive the PHASERREFCLK input of the PHASER_IN or the PHASER_OUT. The PHASER_IN provides the CLK and CLKDIV inputs for the ISERDES, and the PHASER_OUT provides the CLKB input for the ISERDES.

When a QDRII+ component has 2.0 cycle read latency, CQ will be used to sample rising edge data and CQ# for falling edge data. When QDRII+ component has 2.5 cycles read latency, CQ# will be for rising edge data and CQ for falling edge data.

AR# 51567
Date Created 08/30/2012
Last Updated 09/05/2012
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • ISE Design Suite - 14.2
  • Memory Interface and Controller