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AR# 51602

14.x Constraints - How to create basic RPMs with the placement constraints

Description

How can I create basic RPMs with the XilinxISE constraints? Is thereanybasic example designwhereto findout how to use them in aeasyway?

Solution

The most basic RPMs are made of same type of primitives: Flip-Flops+LUTs or RAMs or DSPs, but these objects can also be combined. This articlepresents a basic way to create those RPMs for the primitives mentioned and how the related constraints work.

There area fewbasic constraints to create RPMs:
- RLOC: It is used to pass on the location information to the instantiated primitives. This location can be relative to a specific starting point of coordinates orthe primitives which form the RPM group.
- U_SET: User defined RPM name. It must be same name for all members of a RPM group.
- RLOC_ORIGIN: It sets up the reference starting coordinates for all members of a RPM group, if the primitives have to be placed in a specific location of the FPGA.
In other words, this value is added to the RLOC value to determine the exact location of the elements of the RPM. Finall_location = RLOC_ORIGIN + RLOC.
- RPM_GRID: Thisoption enables theabsolute path forLocation values defined in the "FPGA editor," like (RPM grid X_Y_)
- RLOC_RANGE: Allows the userto specify a region of the FPGA instead of a starting coordinate. This gives more freedom for the tools to place the components.

With the following examples, it is easier to understand the performance of these constraints:

Example 1
INST "out_val_6" U_SET=FF_rpm3;
INST "out_val_7" U_SET=FF_rpm3;
INST "out_val_6" RLOC= X0Y0;
INST "out_val_7" RLOC=X2Y1;

This example placestwo Flip-Flops anywhere in the FPGA, but keeps a relation between the slices which contain the modules of X2-X0= X2 ; Y1-Y0= Y1.

FPGA Editor values placement of "out_val_6"at site X0Y93
placemnt_ff_rpm3_a.png
FPGA Editor values placement of "out_val_6"at site X2Y94 = X0Y93 + X2Y1
placemnt_ff_rpm3_b.png

Example 2:DSP modules placed with absolute path
INST "Maddsub_mult_val_mult00001" U_SET=dsp_rpm2; ###DSP_1
INST "Maddsub_mult_val_mult00002" U_SET=dsp_rpm2; ###DSP_2
INST "Maddsub_mult_val_mult00001" RLOC=X49Y0 | RPM_GRID = GRID | RLOC_ORIGIN=X0Y0;
INST "Maddsub_mult_val_mult00002" RLOC=X49Y5;

This example uses the absolute path in the FPGA, so the components must be placed in the right location, otherwise an error message will be issued by NGDBUILD if the primitive can not be placed because the location does not represent a valid location for the primitive.
The values for placing the components when RPM_GRID = GRID is used are represented in the FPGA editor like: site "DSP48_X0Y37", type = DSP48E (RPM grid X37Y185)
RLOC_ORIGIN represents the starting point of the coordinates. It is recommended to use always RLOC_ORIGIN=X0Y0 when RPM_GRID = GRID is applied so no confusion is generated with the locations.

Example3: Combination of DSP + Flip-Flops + LUTs placed with absolute path
INST "Maddsub_mult_val_mult00003" U_SET=dsp_ff_logic__rpm |RLOC =X73Y15 | RPM_GRID = GRID | RLOC_ORIGIN=X0Y0; ### DSP module
INST "out_val_4" U_SET=dsp_ff_logic__rpm | RLOC =X69Y12; ### FF_1
INST "out_val_5" U_SET=dsp_ff_logic__rpm | RLOC =X79Y16; ### FF_2
INST "out_val_2_cmp_eq00001" U_SET=dsp_ff_logic__rpm | RLOC =X69Y12; ### LUT_1
INST "out_val_3_cmp_eq00001" U_SET=dsp_ff_logic__rpm | RLOC =X79Y16; ### LUT_2

When the user wants to place different types of primitives together, then it is mandatory to use the absolute path placement. Use the RPM_GRID = GRID and RLOC_ORIGIN constraints and specify the correct place for each primitive type. LUTs and Flip-Flops are combined in the same SLICES.
placemnt_ff_luts_dsp_rpm.png


With thisarticle you can find the source code, the UCF file, and a few examples to understand the performance of those constraints

Attachments

Associated Attachments

Name File Size File Type
example_wts.vhd 1 KB VHD
example_wts.ucf 1 KB UCF

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43534 14.x Constraints - How to apply RLOC_RANGE constraints N/A N/A
AR# 51602
Date Created 10/15/2012
Last Updated 03/02/2013
Status Active
Type Design Advisory
Devices
  • FPGA Device Families
Tools
  • ISE Design Suite