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AR# 51667 Xilinx MIG 7 Series Solution Center - Design Assistant - Simulation Debug

Description

This section of the MIG 7 Series Design Assistant focuses on Simulation Debug for MIG 7 Series designs. Please select from the options below to find information related to your specific question.

Note: This article is part of the Xilinx MIGSolution Center (Xilinx Answer 51313). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIGor troubleshooting a problem, use the MIGSolution Center to guide you to the right information.

Solution

The illustration below shows the debug flow for MIG 7 Series designs.
sim_debug.png
sim_debug.png

Forsimulation debug steps for debugging calibration failures of MIG 7 Series designs, please refer to (Xilinx Answer 43879) Hardware Debug Guide.
For simulation debug steps for debugging proper write and read commands, please refer to the "Interfacing with the Core" -> "AXI4 Slave Interface","User Interface","Native Interface", and the"Physical Layer Interface"sections of UG586.
For steps on setting up and simulating the example design, please refer to the "Getting Started with the CORE Generator Tool" -> "Modifying the Example Design" -> "Setting Up for Simulation" section of UG586.

Revision History
09/20/12 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51666 Xilinx MIG 7 Series Solution Center Design Assistant - Simulation N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43879 7 Series MIG DDR3/DDR2 - Hardware Debug Guide N/A N/A

Actions

AR# 51667
Date Created 09/18/2012
Last Updated 09/20/2012
Status Active
Type Solution Center
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series
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