We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 51697

MIG Spartan-6 MCB - Incorrect logic on p1_wr_error assignment


Version Found: 3.91

Version Fixed: Never Fix: This issue is present in ISE14.7 v3.92

In the generated MIG Spartan-6 MCB design, line 3381 of the mcb_raw_wrapper. file incorrectly assigns the p1_wr_error flag as follows:

         assign p1_wr_error    = mig_p5_error | mig_p5_error;


The correct logic should be as follows:

          assign p1_wr_error    = mig_p3_error | mig_p5_error;

This is because the write path of the second port uses p3 and p5.

AR# 51697
Date Created 09/07/2012
Last Updated 04/01/2016
Status Active
Type Known Issues
  • MIG Virtex-6 and Spartan-6