Version Found: v1.04a
Version Resolved and other Known Issues: see (Xilinx Answer 44969)
When I generate a BSB design with AXI Bridge for PCI Express for the KC705 Rev C board, the core is not detected.
The standalone core generated in the CORE Generator tool works without any issue.
This is a known issue to be fixed in a future release of the core.
To work around this issue, follow the steps below: