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AR# 51739

14.3 - XPS - XPS compiler fails with with Simulink pcore on Zynq

Description

EDK project do not compile a Pcore AXI-bus generate with Simulink model
-------------------------------
This is from the Error Message
------------------------------
ERROR:HDLCompiler:1318 - "./EDK/pcores/model_axiw_v1_00_a/hdl/vhdl/model_axiw.vhd" Line 67: Left bound value <11> of slice is out of range [7:0] of array <s_axi_arid>
ERROR:EDK - xst: unknown error occurred.
ERROR:EDK:546 - Aborting XST flow execution!

Solution

The issue here is that the Pcorecreated from System Generator makes HDL code that explicitly sets the parameters for id_width.

There aretwo possible workarounds for this issue:

1) Open the <ip_name>_axiw.vhd in the process directory seen below:

pcores\<ip_name>_axiw_v1_00_a\hdl\vhdl\<ip_name>_axiw.vhd

Changelines 67 to 71 from:

s_axi_arid(C_S_AXI_ID_WIDTH-1 downto 0) <= sg_s_axi_arid;
s_axi_awid(C_S_AXI_ID_WIDTH-1 downto 0) <= sg_s_axi_awid;

sg_s_axi_rid <= s_axi_rid(C_S_AXI_ID_WIDTH-1 downto 0);
sg_s_axi_bid <= s_axi_bid(C_S_AXI_ID_WIDTH-1 downto 0);

to:

axiaddrpref_less: if (C_S_AXI_ID_WIDTH <= C_S_AXI_NATIVE_ID_WIDTH) generate
s_axi_arid(C_S_AXI_ID_WIDTH-1 downto 0) <= sg_s_axi_arid;
s_axi_awid(C_S_AXI_ID_WIDTH-1 downto 0) <= sg_s_axi_awid;
sg_s_axi_rid <= s_axi_rid(C_S_AXI_ID_WIDTH-1 downto 0);
sg_s_axi_bid <= s_axi_bid(C_S_AXI_ID_WIDTH-1 downto 0);
end generate axiaddrpref_less;
axiaddrpref_greater: if (C_S_AXI_ID_WIDTH > C_S_AXI_NATIVE_ID_WIDTH) generate
s_axi_arid <= sg_s_axi_arid(C_S_AXI_NATIVE_ID_WIDTH-1 downto 0);
s_axi_awid <= sg_s_axi_awid(C_S_AXI_NATIVE_ID_WIDTH-1 downto 0);
sg_s_axi_rid(C_S_AXI_NATIVE_ID_WIDTH-1 downto 0) <= s_axi_rid;
sg_s_axi_bid(C_S_AXI_NATIVE_ID_WIDTH-1 downto 0) <= s_axi_bid;
-- Set upper 4 bits to 1000 for general performance, 0000 for high performance
sg_s_axi_rid(C_S_AXI_ID_WIDTH - 1 downto C_S_AXI_ID_WIDTH - 4) <= "1000";
sg_s_axi_bid(C_S_AXI_ID_WIDTH - 1 downto C_S_AXI_ID_WIDTH - 4) <= "1000";
end generate axiaddrpref_greater;

Once this is done,Rescan theUser Repository:

refresh.png
refresh.png

The IP should pass through the tools now without issue. It is likely you may get a Bitgen error if your System Generator pcore contains I/O portsthat have not been LOC'ed in the UCF.

2) Alternatively, there is a patch available for System Generator which can be requested through Xilinx Technical Support. Please open a Webcase to request the patch.

AR# 51739
Date Created 09/11/2012
Last Updated 11/27/2012
Status Active
Type General Article
Tools
  • EDK - 14.1
  • EDK - 14.2
  • EDK - 14.3