We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 51744

Zynq-7000, Vivado - How Do I Change ODT Values for the Zynq-7000 PS DDR Controller?


How do I set ODT values for the for the Zynq PS7 DDR Controller?

(UG585), states that the ODT values can be changed:

"10.6.6 DRAM Input Impedance (ODT) Calibration
The on-die-termination (ODT) is available in DDR2 and DDR3 devices with the following features:
In DDR3 devices, the ODT value is controlled via Mode register MR1. It can be disabled, or set to one of the following values: 120, 60, or 40.
In DDR2 devices, the ODT value is controlled via the mode register EMR. It can be disabled, or set to one of the following values: 75, 150, or 50.
Both DDR2 and DDR3 devices have a dedicated ODT input pin that is used to enable the ODT during write operations, and disable it otherwise."


Vivado does not allow you to change ODT values from the GUI.

To change the ODT values for DDR3, you must change the MR1 register manually in the ps7_init.tcl and/or ps7_init.c files.

The following register names correspond to the following MR registers:


  • Bit 15:0 (reg_ddrc_mr) is MR0
  • Bit 31:16 (reg_ddrc_emr) is MR1


  • Bit 15:0 (reg_ddrc_emr2) is MR2
  • Bit 31:16 (reg_ddrc_emr3) is MR3

The values are in hexadecimal.

The bit definition for MR# registers can be found in the DRAM datasheet.

AR# 51744
Date Created 09/11/2012
Last Updated 11/20/2015
Status Active
Type General Article
  • Zynq-7000
  • Vivado Design Suite - 2012.1
  • Vivado Design Suite - 2012.2
  • Processing System 7