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AR# 51782

EDK-14.3,Zynq-7000 - What is the default QSPI interface clock frequency used in the FSBL and how do I speed it up?

Description

When booting in QSPI mode, what is theQSPI interface clock frequency while the FSBL (14.3) is executing?

What if I want to increase that frequency because my board is capable of higher frequency on the QSPI interface clock?

Solution

XPS lets you choose the QSPI reference clock (maximum frequency is 200 MHz).

The FSBL in the function InitQspi() in the module qspi.c sets the following defaults:

- Change the baud rate to DIV/8 prescaler value
- Set the USE loopback bit ( but the loopback is actually disabled because the prescaler is not DIV/2 )

For Example, if the QSPI reference clock is 200 MHz, the default QSPI interface clock will be 25 MHz.

If you want to speed up the QSPI interface clock, simply change the divider prescaler to DIV/4 or DIV/2 in your FSBL.

Note: If DIV/2 is selected, the loopback automatically enables because the loopback bit is set.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
52540 Zynq-7000 AP SoC - Frequently Asked Questions N/A N/A
AR# 51782
Date Created 09/12/2012
Last Updated 10/25/2012
Status Active
Type General Article
Devices
  • Zynq-7000
Tools
  • EDK - 14.3