Example that flashes LEDs on the ZC702: 2 MIO LEDs, 4 EMIO LEDs and 4 AXI LEDs.
Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000. A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools. It is up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill his needs. Limited support is provided by Xilinx on these Example Designs.
Implementation Details
| Design Type |
PS and PL |
|---|
| SW Type |
Standalone |
|---|
| CPUs |
Single CPU |
|---|
| PS Features |
UART, GPIO |
|---|
| PL Cores |
AXI GPIO SLAVE |
|---|
| Boards/Tools |
ZC702 |
|---|
| Xilinx Tools Version |
EDK 14.1 |
|---|
| Other details |
-- |
|---|
| Address Map |
|---|
|
Base Address |
Size |
Bus Interface |
|---|
| AXI GPIO |
0x41200000 |
64K |
S_AXI |
|---|
| PS UART1 |
0xE0001000 |
4K |
MIO |
|---|
| PS GPIO |
0xE000A000 |
4K |
MIO/EMIO |
|---|
| Files Provided |
|---|
| gio_mio_emio_axi.zip |
Archived PlanAhead project. |
|---|
Note: A version of the design built using Vivado IP Integrator is also attached.
- Simply, create a new Vivado project targeting the ZC702.
- Source the .tcl to create the block design.
- Add the constraints files.
- Generate the output products.
- Create the HDL wrapper and generate the bitstream.