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AR# 51787

Zynq-7000 AP SoC - Questions about debug resets

Description

The reset behavior on the Zynq-7000 AP SoC family while debugging varies depending on the version of silicon.

Solution

Silicon Behavior

1.0 Silicon

  • JTAG and debug system are disabled on initial power on. They are enabled after the BootROM runs to completion.
  • On soft reset, JTAG and debug system remain enabled.

2.0 Silicon

  • JTAG and debug system are disabled on initial power on. They are enabled after the BootROM runs to completion.
  • On soft reset, JTAG is disabled but debug system remains enabled.

Production Silicon

  • JTAG and debug system are disabled on initial power on. They are enabled after the BootROM runs to completion.
  • On soft reset, JTAG and debug system are disabled.

Consequences of Silicon Behavior

1.0

  • If a vector catch is set or a breakpoint is set within the memory region that the BootROM executes from (0x0 to 0x40000), the processor will stop at that breakpoint after reset since the debug system is enabled.
  • If the processor stops before the BootROM runs to completion, the memory map will not appear as it should post-BootROM.
  • The processor needs to be allowed to continue till the BootROM has finished execution. This is possible since JTAG and the debug system are enabled.

2.0

  • If a vector catch is set or a breakpoint is set within the memory region that the BootROM executes from (0x0 to 0x40000), the processor will stop at that breakpoint after reset since the debug system is enabled.
  • It is not possible to resume the processor after a breakpoint is hit because JTAG is disabled.

Production Silicon

  • Vector catch and breakpoint within the memory region that the BootROM executes from (0x0 to 0x40000) are disabled during BootROM execution.
  • The boot ROM will then re-enable the debug system along with the JTAG upon exit, which will re-activate any breakpoints/vector catch that were set before the soft reset and will apply them to the user application or FSBL.

Software Behavior

In order to work around the reset behavior, Xilinx Microprocessor Debugger (XMD) implements a software work-around (for 1.0 and 2.0 Silicon) to make the reset behavior consistent.

Before reset, a piece of code is loaded to the Zynq-7000 AP SoC which performs the following operations:.

  • The debug system and JTAG are disabled.
  • A breakpoint is set to catch the exit from the BootROM.
  • The processor is reset.

The BootROM always enables the debug system and JTAG on exit if the image is a non-secure image regardless of the boot mode setting. This allows the BootROM to execute (since the debug system is disabled) and allows the processor to stop before user code is executed.

NOTE: The work-around is NOT needed for Production Silicon.

Software Consequences on 1.0 and 2.0 Silicon

Because the software needs to execute a piece of code prior to device reset, there is one main consequence:

  • If the processor is hung, reset will not be able to recover the processor.
  • This means that if, for example, the boot mode is set to QSPI but a bad image was programmed that hangs the processor, XMD will not be able to recover because it will be unable to stop the processor before the user code (programmed to QSPI) executes.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
52538 Zynq-7000 AP SoC - Boot and Configuration N/A N/A
AR# 51787
Date Created 11/20/2012
Last Updated 10/30/2013
Status Active
Type General Article
Devices
  • Zynq-7000
Tools
  • EDK - 14.2
Boards & Kits
  • Zynq-7000 All Programmable SoC ZC702 Evaluation Kit