UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 51790

Zynq-7000 - How is the DDRC address mapping used?

Description

How is the Zynq-7000 DDR Controller address mapping used to convert from an AXI address to the DRAM addressing?

Solution

Generally, the Xilinx design tools provide a default Row/Bank/Column addressing arrangement, and should be used for most cases.

The document attached to the end of this answer record provides an example configuration of the address mapping used.

Attachments

Associated Attachments

Name File Size File Type
Zynq_DDRC_Addressing.pdf 328 KB PDF

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
52540 Zynq-7000 AP SoC - Frequently Asked Questions N/A N/A
53051 Zynq-7000 AP SoC - PS DDR Controller N/A N/A
AR# 51790
Date Created 09/13/2012
Last Updated 03/02/2013
Status Active
Type General Article
Devices
  • Zynq-7000