51790

How is the Zynq-7000 DDR Controller address mapping used to convert from an AXI address to the DRAM addressing?

Generally, the Xilinx design tools provide a default Row/Bank/Column addressing arrangement, and should be used for most cases.

The document attached to the end of this answer record provides an example configuration of the address mapping used.

Name	File Size	File Type
Zynq_DDRC_Addressing.pdf	328 KB	PDF

Answer Number	Answer Title	Version Found	Version Resolved
52540	Zynq-7000 AP SoC - Frequently Asked Questions	N/A	N/A
53051	Zynq-7000 AP SoC - PS DDR Controller	N/A	N/A

AR# 51790 Zynq-7000 - How is the DDRC address mapping used?