SystemVerilog Packages structures that are supported by Vivado Synthesis
Please refer to Table 1-1 at the end of this AR for the related coding examples.
Packages provide an additional way to share different constructs. They have similar behavior to VHDL packages. Packages can contain many things, for example, functions, tasks, types, enums. Packages are referenced in other modules by the import command.
Coding Examples for Packages
|Coding Example Name
||Constructs Used |
- enum, logic data type and user-defined data type
- automatic function and void function
- case statement
- always_ff procedural block
- operator: +, -, *, =