AR# 51878 Zynq-7000 Debug - Routing PJTAG to the Mictor connector on FMC-105 attached on ZC702
Description
This example design uses the FMC1 connector on the ZC702 board to attach the XILINX HW_FMC-105-DEBUG board. The TRACE port gets routed via EMIO to the Mictor connector on the FMC-105. Also, the PJTAG is routed via EMIO on J16 to the mezzanine board and then wired to J19. The result is that a debugger (for example Lauterbach) can use the JTAG connection available on the Mictor connector.
Solution
Implementation Details
Files Provided
- Simply, create a new Vivado project targeting the ZC702.
- Source the .tcl to create the block design.
- Add the constraints files.
- Generate the output products.
- Create the HDL wrapper and generate the bitstream.
Note: The Lauterbach POD checks if power is present on PIN 14 of the Mictor connector. The FMC-105 card has PIN 14 not connected. Shorting together PIN 12 and 14 on the FMC-105 is necessary to connect PIN 14 to VADJ and PASS the Lauterbach check of the power.
Step by Step Instructions
1. Setup the connection on the board as shown in the attached picture.
TCK => J16-6 => FMC1_LA30_P => E21 on the Zynq BANK.
TMS => J16-8 => FMC1_LA30_N => D21 on the Zynq BANK.
TDI => J16-10 => FMC1_LA31_P => A16 on the Zynq BANK.
TDO => J16-12 => FMC1_LA31_N => A17 on the Zynq BANK.
2. Generate a bitstream from the attached XPS project ( Note PJTAG routing in system.ucf ).
3. Build a BOOT.bin containing the FSBL + system.bit + u-boot
4. Copy your BOOT.bin on the SD card
5. Boot from SD card and Independent JTAG.
6. On the Terminal wait for the u-boot prompt and stop autoboot ( At this time level shifter are enabled ).
7. Connect your debugger to the PJTAG and TRACE port via the Mictor connector.
Setup Picture.
Linked Answer Records
Master Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 50863 | Zynq-7000 AP SoC - Debug | N/A | N/A |