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AR# 51885

14.2 - Zynq - DDR2 Drive Strength and Slew Rate Registers

Description

The following signals in the TRM -

DDRIOB_DRIVE_SLEW_ADDR
DDRIOB_DRIVE_SLEW_DATA
DDRIOB_DRIVE_SLEW_IFF
DDRIOB_DRIVE_SLEW_CLOCK

What would be the result of modifying these signals?

Solution

Changing the values of these registers will have unknown effects on I/Os and may cause non-compliance to JEDEC standards, making IBIS models inaccurate as well as causing reliability issues. Therefore, the encoding of these registers is not documented.

The TRM is being revised to have these fields reserved and state that these registers should not be modified from the setting provided in EDK.
AR# 51885
Date Created 11/26/2012
Last Updated 01/30/2013
Status Active
Type General Article
IP
  • Memory Interface and Controller
Boards & Kits
  • Zynq-7000 All Programmable SoC Boards and Kits