To begin debugging a suspected hardware issue on the ZC706, see (Xilinx Answer 54013) - Zynq-7000 AP SoC ZC706 Evaluation Kit - Board Debug Checklist.
The ZC706 Board Debug Checklist forms part of (Xilinx Answer 43745) - Xilinx Boards and Kits Solution Center. Board and Kit Related Issues
KNOWN ISSUES:
Board and Kit Related Issues
(Xilinx Answer 53305) - Zynq-7000 AP SoC ZC706 Evaluation Kit - SD card is empty
(Xilinx Answer 53174) - Zynq-7000 AP SoC ZC706 Evaluation Kit - Kits shipped without ATX (PCIe) MiniFit Jr. adapter
Documentation Related Issues
(Xilinx Answer 52344) - Zynq-7000 SoC ZC706 Evaluation Kit - Which SD Interface Level Shifter is present on the ZC706 Evaluation Platform?
(Xilinx Answer 53453) - Zynq-7000 AP SoC ZC706 Evaluation Kit - UG954 - GPIO_LED_0 not listed in Table 1-27
(Xilinx Answer 53862) - Zynq-7000 AP SoC ZC706 Evaluation Kit - SW4 settings for the ZC706
(Xilinx Answer 53863) - Zynq-7000 AP SoC ZC706 Evaluation Kit - UG961 (v1.0) - SW4 settings to run the BIST on the ZC706
(Xilinx Answer 54036) - Zynq-7000 AP SoC ZC706 - UG963 (v1.0) - SW11 switch settings incorrect for SD card boot
(Xilinx Answer 54037) - Zynq-7000 AP SoC ZC706 - UG961 (v1.0) - SW11 switch settings incorrect for SD card boot
(Xilinx Answer 54105) - Zynq-7000 AP SoC ZC706 - UG954 (v1.1) - ZC706 inconsistent pin assignments on FMC connector Table 1-33
(Xilinx Answer 55184) - Zynq-7000 AP SoC ZC706 Evaluation Kit - What is the I2C bus address for the PMBUS_DATA/CLOCK signal?
Silicon Related Issues
(Xilinx Answer 47915) - Design Advisory Master Answer Record for Zynq-7000 AP SoC Devices
PCI Express Related Issues
(Xilinx Answer 52656) - Zynq AP SoC ZC706 Evaluation Kit - PCIe Targeted Reference Design - PCIe does not link up on Z77 (Ivy Bridge) platform
(Xilinx Answer 53740) - Design Advisory for 7 Series Xilinx PCI Express Cores - No Clock Output on TXOUTCLK at Cold Temperature
Design Tools Related Issues
(Xilinx Answer 52071) - Zynq-7000 SoC AP Impact - QSPI programming on the ZC706 (7045) requires the board to be in JTAG mode
USEFUL INFORMATION:
Third Party Debug Tool Information
(Xilinx Answer 46881) Zynq-7000 - How to setup your Third Party Debug Environment on the ZC702 Board
(Xilinx Answer 47767) Zynq-7000, ZC702 - Lauterbach Startup Script
Reference Design Information
(Xilinx Answer 46880) Zynq-7000 Example Design - Linear QSPI Performance (Max Effective Throughput)
(Xilinx Answer 46915) Zynq-7000 Example Design - Setup the TRACE port via EMIO on the ZC702 board
(Xilinx Answer 50572) Zynq-7000 Example Design - Interrupt handling of PL generated interrupt
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 43750 | Xilinx Boards and Kits Solution Center - Top Issues | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 54013 | Zynq-7000 AP SoC ZC706 Evaluation Kit - Board Debug Checklist | N/A | N/A |
| 47915 | Design Advisory Master Answer Record for Zynq-7000 AP SoC Devices | N/A | N/A |