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AR# 51901

Virtex-7 FPGA VC709 Connectivity Kit - Known Issues and Release Notes Master Answer Record

Description

This answer record lists all known issues with the Virtex-7 FPGA VC709 Connectivity Kit.

Solution

To view the Design Advisories associated with the VC709 kit, see (Xilinx Answer 56324) Design Advisory Master Answer Record for Virtex-7 FPGA VC709 Evaluation Kit.

Customers are advised to use the latest version of the Targeted Reference Design (2014.3).

  • If using this Connectivity Kit for legacy purposes, customers must adhere to (Xilinx Answer 59167) Design Advisory for MIG 7 Series DDR3 - Data rate specification changes for DIMM interfaces and data rate advisory for component interfaces.
  • To identify the silicon on your VC709, please see (Xilinx Answer 37579).
  • To begin debugging a suspected hardware issue on the VC709, see (Xilinx Answer 54355) Virtex-7 FPGA VC709 Connectivity Kit - Board Debug Checklist.

The VC709 Board Debug Checklist and VC709 Design Advisory Master Answer Record form part of (Xilinx Answer 43745) Xilinx Boards and Kits Solution Center - available to address all questions related to Xilinx Boards and Kits.

Board and Kit Related Issues

(Xilinx Answer 37579)Which device do I have on my Xilinx Evaluation Kit? Is it Engineering Sample (ES) or Production Silicon?
(Xilinx Answer 43514)Development Boards - Device on board does not match schematic
(Xilinx Answer 45380)Development Boards - Xilinx PCIe form factor board TI power system cooling
(Xilinx Answer 50596)Xilinx Evaluation Kits - PCIe cards - CE Requirements for PC Test Environment
(Xilinx Answer 54022)How can I order a TI USB Interface Adapter EVM from Texas Instruments?
(Xilinx Answer 55805)Xilinx Evaluation Kits - Board becomes non-operational when TI USB Interface EVM is attached
(Xilinx Answer 56695)Virtex-7 FPGA Connectivity Kit - SODIMM pinout
(Xilinx Answer 57618)Virtex-7 FPGA VC709 Connectivity Kit - What is the SODIMM capacity of the VC709?
(Xilinx Answer 58082)Virtex-7 FPGA VC709 Connectivity Kit - TRD Release Notes
(Xilinx Answer 59754)Virtex-7 FPGA VC709 Connectivity Kit - PCB Revision Differences
(Xilinx Answer 61849)6 Series and 7 Series Xilinx Evaluation Kit - Known Issues and Release Notes Master Answer Record for the Texas Instruments Power Solution
(Xilinx Answer 66509)7 Series and UltraScale Kits - Interaction with ADI AD9625-2.5EBZ FMC card
(Xilinx Answer 67507)Xilinx Boards and Kits - Power Supply Information

Documentation Related Issues

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 56382)UG887 (v1.1) VC709 Evaluation Board for the Virtex-7 FPGA User Guide - Table 1-20 lists incorrect pin connection for FMC1_HPC_LA29_Nv1.1v1.2
(Xilinx Answer 58912)Boards and Kits - Board files blocked on xilinx.com
(Xilinx Answer 60426)UG887 (v1.2) VC709 Evaluation Board for the Virtex-7 FPGA User Guide - Table 1-20 lists incorrect FMC connector designationv1.2v1.3
(Xilinx Answer 67573)Virtex-7 FPGA VC709 Connectivity Kit - UG887 (v1.5) - Table 1-6 U1 Pin for Flash address is incorrectv1.5v1.5.1

PCI Express / IP Related Issues

(Xilinx Answer 40469)7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions
(Xilinx Answer 47441)Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions
(Xilinx Answer 53371)Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.4 (ISE 14.4) - Support for VC709 Xilinx Development Boards
(Xilinx Answer 57777)Virtex-7 FPGA Gen3 Integrated Block for PCI Express - COMMON_CFG Attribute update for Production Silicon
(Xilinx Answer 54643)7 Series Integrated Block for PCI Express - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions
(Xilinx Answer 59167)Design Advisory for MIG 7 Series DDR3 - Data rate specification changes for DIMM interfaces and data rate advisory for component interfaces

Design Tools Related Issues

(Xilinx Answer 46253)ChipScope IBERT - Virtex-6, Kintex-7, Virtex-7 - 12 MHz cable speed does not work with IBERT
(Xilinx Answer 47816)7 Series - ISE 14.x/Vivado 2012.2 Design Suite Known Issues Related to 7 Series FPGA
(Xilinx Answer 50906)Design Advisory for Production Kintex-7 325T, 410T, 420T and Virtex-7 485XT, 690XT - Bitstream compatibility requirements between GES and Production
(Xilinx Answer 55402)iMPACT 14.3/4/5 - VC709 - Virtex-7 690T - BPI Indirect Programming fails with " '0': Errors encountered while loading microprogram"
(Xilinx Answer 55456)2012.4 - Virtex-7 FPGA VC709 Connectivity Kit - Targeted Reference Design Release Information
(Xilinx Answer 55534)Virtex-7 FPGA VC709 Connectivity Kit - Is there a Targeted Reference Design for 2013.1 available?
(Xilinx Answer 55931)Xilinx Evaluation Kits - What type of license is shipped with Xilinx Evaluation Kits?
(Xilinx Answer 56332)Design Advisory for Virtex-7 GTH - QPLL Attribute Updates for Production Silicon
(Xilinx Answer 57325)VC709 FPGA Connectivity Kit 2013.2 TRD - Users may encounter an error when simulating the Design using ModelSim

 

Linked Answer Records

Child Answer Records

AR# 51901
Date Created 09/19/2012
Last Updated 08/25/2016
Status Active
Type Known Issues
Boards & Kits
  • Virtex-7 Boards and Kits
  • Virtex-7 FPGA VC709 Connectivity Kit