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AR# 51950

Tandem PCIe Second Stage Bitstream Loading Across the PCI Express Link


This answer record provides a PDF document describing the second stage bitstream loading across the PCI Express Link with Tandem PCIe. 

The associated files have also been provided in a ZIP file.

The provided mechanism to load second stage bitstream Tandem PCIe is applicable for both 7 Series Integrated Block for PCI Express and Virtex-7 FPGA Gen3 Integrated Block for PCI Express cores.

For bitstream loading across the PCI Express link in UltraScale Devices for Tandem PCIe and Partial Reconfiguration, please refer to (Xilinx Answer 64761).


Please download the "Tandem PCIe Second Stage Bitstream Loading across the PCI Express Link" PDF and the associated design files at the end of this answer record.

The file names are:

  • Xilinx_Answer_51950.pdf
  • Xilinx_Answer_51950_Files.zip

Note: When configuring the core with larger BAR size (for example, 128MB) and Tandem PCIe enabled, the second stage bitstream programming can fail with the driver stating "Located 0 FPC Device". 

In order to resolve this issue, please apply the fix provided in (Xilinx Answer 60606).

Revision History:

12/18/2012 - Initial release
08/29/2013 - Updated for Windows Environment
09/12/2013 - Added Tandem Software Flow and Tandem KC705 Example Flow in the PDF.
05/28/2014 - Added information on issue reported in (Xilinx Answer 60606)
06/30/2015 - Added reference to (Xilinx Answer 64761)


Associated Attachments

Name File Size File Type
Xilinx_Answer_51950.pdf 546 KB PDF
Xilinx_Answer_51950_Files.zip 48 KB ZIP
AR# 51950
Date Created 12/17/2012
Last Updated 06/30/2015
Status Active
Type General Article
  • 7 Series Integrated Block for PCI Express (PCIe)