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AR# 51954

MIG 7 Series DDR2/DDR3 - PHY Initialization and Calibration


The MIG 7 Series DDR2/DDR3 PHY logic contains state logic for initializing the SDRAM memory after power-up and performs timing training of the read and write data paths to account for system static and dynamic delays.This section of the MIG Design Assistant focuses on the initialization and calibration (timing training) performed by the PHY at power-up.
The 7 Series FPGAs Memory Interface Solutions User Guide (UG586) includes a detailed section on the PHY logic. Please review this material within the DDR2/DDR3 SDRAM Memory Interface Solution > Core Architecture >PHY section:
Note: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


The following diagram shows the7 SeriesPHY sequence for initialization and calibration:
7 series calib.JPG
7 series calib.JPG

When calibration completes successfully, init_calib_complete asserts. The below section includes information on these stages and common calibration questions. For detailed information on each stage, see the PHY section of UG586.
DDR SDRAM Initialization (Xilinx Answer 34744)
During this stage of calibration, each PHASER_IN is placed in the read calibration mode to phase align its free-running frequency reference clock to the associated read DQS. The calibration logic issues back-to-back read commands to provide the PHAESER_IN block with a continuous stream of DQS pulses for it to achieve lock. Each DQS has an associated PHASER_IN block. Dbg_pi_phase_locked asserts when all PHASER_INs have achieved lock and the PHASER_INs are then placed in normal operation mode.


In this stage of calibration, the different DQS groups are aligned to the same PHY_Clk and the optimal read data offset position is found with respect to the read command. The calibration logic issues a set of four back-to-back reads with gaps in between. Each Phaser_IN detects the read DQS preamble. A single read data offset value is determined for all DQS groups. This data offset is then used during read requests to the PHY_CONTROL block.

Write Leveling - DDR3 Only

Write leveling, a new feature in DDR3 SDRAMs, allows the controller to adjust each write DQS phase independently with respect to the CK forwarded to the DDR3 SDRAM device. This compensates for the skew between DQS and CK and meets the tDQSS specification. During this stage, the PHY logic asserts the Write_Calib_N input to the PHY Control Block to indicate the start of write leveling. Periodic write requests are issued to the PHY Control Block to generate periodic DQS pulses. The PHASER_IN outputs a free-running clock to capture the DQ feedback into the DQ IN_FIFOs. The PHASER_OUT fine and coarse taps are used to phase shift DQS one tap at a time until a 0-to-1 transition is seen on the feedback DQ.

Write Leveling is performed at three different points during the calibration process. After memory initialization completes, the PHASER_OUT fine and coarse taps are set to zero. Write Leveling is then initially performed to align DQS to CK. After OCLKDELAYED calibration completes, the coarse tap values found during the initial Write Leveling are carried over and the fine taps are reset to zero. Write Leveling is performed again to ensure the DQS-to-CK relationship is still correct. Finally, during Write Calibration both the fine and coarse delays are carried over and final adjustments are made when necessary. During Write Calibration, the appropriate pattern must be detected. If Write Leveling aligned DQS to the wrong CK clock, final PHASER_OUT fine/coarse delay adjustments are required to move DQS up to two CK clock cycles.
(Xilinx Answer 35094) Additional Write Leveling Information

MPR Read Leveling Failures - DDR3 Only
At this stage of calibration, the write DQS is not centered in the write DQ window, nor is the read DQS centered in the read DQ window. The DDR3 Multi-Purpose Register (MPR) is used to center the read DQS in the read DQ window. The MPR has a pre-defined 01010101 or 10101010 pattern that is read back during this stage of calibration. The read DQS centering is required for the next stage of calibration, OCLKDELAYED calibration.

(Xilinx Answer 34359) JEDEC Specification - Multi-Purpose Register

OCLKDELAYED Calibration - DDR3 Only
This stage of calibration centers the write DQS in the write DQ window. This centering is accomplished using the PHASER_OUT stage 3 delay line. The starting stage 3 tap value is 30. The taps are first decremented until either an edge is found or the tap value reaches 0. The stage 3 taps are then incremented back to 30 and edge detection begins increasing from 31 until either an edge is found, or the tap value reaches 63. The center point is then computed based on the detected edges and the stage 3 taps are decremented to the computed value.

Note that with every decrement of stage 3 tap the stage 2 taps are incremented by 2 to maintain the appropriate DQS to CK relationship established during write leveling. Similarly, with every increment of stage 3 tap, the stage 2 taps are decremented by 2. If stage 2 taps reach 0 or 63, stage 3 tap increment/decrement is allowed to proceed only 15 more times to avoid tDQSS violation. At the end of this stage of calibration, write leveling is re-performed to align DQS and CK using stage 2 taps.

Write Calibration
Write calibration is required to align DQS to the correct CK edge. During write leveling, DQS is aligned to the nearest rising edge of CK. However, this might not be the edge that captures the write command. Depending on the interface type (UDIMM, RDIMM, or component), the DQS could either be one CK cycle earlier than, two CK cycles earlier than, or aligned to the CK edge that captures the write command.

This is a pattern based calibration; hence, multiple writes followed by a single read are issued during this stage. The following data patterns might be seen:
- On time write pattern read back: FF00AA5555AA9966
- One CK early write pattern read back: AA5555AA9966BB11
- Two CK early write pattern read back: 55AA9966BB11EE44
- One CK late write pattern read back: XXXXFF00AA5555AA
--Calibration cannot correct for this pattern. This pattern indicates that the trace delays are incorrect where CK is incorrectly shorter than DQS.

If none of the above patterns are detected during reads, the algorithm assumes the MPR read leveling IDELAY settings are incorrect and the IDELAYs for the DQ bits associated with that byte are set to 0. MPR read leveling could have an incorrect IDELAY setting because with the 01010101 or 10101010 pattern, it is not possible to differentiate between clock cycles.

Read Leveling
The final read DQS to read DQ centering is done in this stage of calibration. The first step in this stage is to decrement the IDELAY and PHASER_IN stage 2 taps values to zero to undo MPR read leveling. MPR read leveling was only required for OCLKDELAYED calibration. This stage of read leveling accurately centers the read DQS in the read DQ window using a 993377EECC992244 data pattern. If this stage calibrates successfully, the init_calib_complete signal is asserted and calibration is complete.

PRBS Read Leveling - Added in MIG 1.7
This stage of calibration determines the read data valid window using a 128 long PRBS sequence (generated through 64-bit LFSR logic) that is written once and readback continuously from the DDR3 SDRAM. The algorithm starts at the DQS PHASER_IN fine tap setting determined during the Read Leveling calibration stage (initial tap value) and decrements one tap at time until a data mismatch is found when comparing read data with the expected data. Note that the expected data is generated using the same 64-bit LFSR logic that was used to write the 128 long PRBS sequence to the SDRAM. The data mismatch tap value is recorded as the left edge. The algorithm then increments to the initial tap value and edge detection begins with every increment after the initial tap value until a data mismatch is found or the tap value is 63. The algorithm then computes the center of the read data valid window based on the detected edges.
Additional Information
(Xilinx Answer 51687) Temperature Monitor Calibration - Added in MIG 1.7
(Xilinx Answer 43344) Dynamic Calibration and Periodic Reads
(Xilinx Answer 43879) Hardware Debug Guide
(Xilinx Answer 35163) Per-bit Deskew

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AR# 51954
Date Created 09/26/2012
Last Updated 03/01/2013
Status Active
Type Solution Center
  • Artix-7
  • Virtex-7
  • Kintex-7
  • MIG 7 Series