What are the Zynq Processing System DDR data sheet parameters? I would like to perform Hyperlynx simulation and board-level timing budget.
TheZynqProcessing System DDR controller does not yet have data sheet numbers available. A schedule will be posted here when it becomes available.
In the meantime, PS DDR board-level design should follow the restrictions from UG933, Zynq-7000 All Programmable SoC PCB Design and Pin Planning Guide.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 52540 | Zynq-7000 AP SoC - Frequently Asked Questions | N/A | N/A |
| 52539 | Zynq-7000 AP SoC - Board Design | N/A | N/A |
| 53051 | Zynq-7000 AP SoC - PS DDR Controller | N/A | N/A |