If I add debug cores to a design in Vivado, the design has the potential to error out due to the 260-character path limit.
For example, if I am working in the Vivado 2012.2 tools on the example MIG DDR3 design targeting a Virtex-7 device, the following error occurs when I add the "debug core" to my design :
WARNING: [Coretcl 2-203] Allowing create_ip to be called on hidden IP: xilinx.com:ip:labtools_xsdb_master_lib:2.0
Generating IP 'debug_core_hub_CV'...
Delivering 'Synthesis' files for IP 'debug_core_hub_CV'.
Error encountered during generation and synthesis of xilinx.com:ip:labtools_xsdb_master_lib:2.0 IP:
ERROR: [Common 17-143] Path length exceeds 260-Byte maximum allowed by Windows
c:/test_Xilinx/design_location/directory_location/Designs/Vivado_Designs/my_designed/test/project_1/project_1.runs/impl_1/.Xil/Vivado-6812-/debug_core_hub_CV_68121348238945/debug_core_hub_CV.srcs/sources_1/ip/debug_core_hub_CV/blk_mem_gen_v7_1/blk_mem_gen_v7_1_xst_comp.vhd
Implementing also fails at the beginning of the implementation flow.
Why is this happening?