We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 52014

Zynq-7000 AP SoC, Boot IOP - Quad-SPI MIO pin 8 is inadvertently enabled during boot


The Quad-SPI I/O interface can optionally use MIO pin 8 as a feedback output clock to enable the interface to be clocked at high frequency. The BootROM inadvertently and unnecessarily enables MIO pin 8 as a toggling output during a Quad-SPI boot sequence.


The BootROM operates the Quad-SPI below the frequency where the feedback output clock is required. The MIO pin 8 is actively driven with the Quad-SPI clock toggling High and Low. The feedback output clock must be allowed to freely toggle.

Board designs should account for MIO pin 8 being an output that toggles during a Quad-SPI boot sequence and take appropriate action.
Configurations Affected:
Systems that use the Quad-SPI boot mode.
Device Revision(s) Affected: Refer to Zynq-7000 Device Advisory Master Answer Record
AR# 52014
Date Created 09/25/2012
Last Updated 10/25/2012
Status Active
Type Design Advisory
  • Zynq-7000