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AR# 52015

Zynq-7000 AP SoC, SPI/Quad-SPI - Quad-SPI register LPBK_DLY_ADJ must be manually set to 0


When the Quad-SPI I/O interface is used with its internal loopback clock, the value of the qspi.LPBK_DLY_ADJ[4:0] register must be set = 0. This field must be set explicitly by the FSBL or the user application.


Impact: Trivial.
Work-Around: When it is the boot device.
Configurations Affected: Systems that use the Quad-SPI interface, but do not boot in Quad-SPI mode.
Device Revision(s) Affected: Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record

AR# 52015
Date Created 09/25/2012
Last Updated 10/25/2012
Status Active
Type Design Advisory
  • Zynq-7000