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AR# 52030

Zynq-7000 AP SoC, Boot Sys - Reset Reason Mechanism does not use slcr.REBOOT_STATUS register

Description

When a device does not support the slcr.REBOOT_STATUS for the reset reason, software must use the de-featured slcr.RESET_REASON register to determine the cause of the last device reset (POR, SRST, debug and other software system resets).

Solution

The software algorithms for determining the reason for the last reset in all silicon revisions are similar, but the register that software uses is different.

The production devices use slcr.REBOOT_STATUS.

Descriptions for production and GES devices are described below.

Impact: Trivial.
Work-around: Software can use the slcr.RESET_REASON register. See Work-around Details.
Configurations Affected: Systems wanting to know the cause of the system reboot.
Device Revision(s) Affected: Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences

 

Operational Details

Processor Reset Source Determination:

The user can determine the source of the most recent reset. The register read and clearing to do this has changed between the Engineering samples (Z-7020 GES and Z-7045 GES devices) and all production devices.:
GES devices: User software must help maintain the state of the slcr.RST_REASON register.
Production: User software must help maintain the state of the slcr.REBOOT_STATUS [22:16] register bits.

The system detects and records the cause of the device reset from 7 possible sources (and recorded in either the RST_REASON or REBOOT_STATUS register):

System Watchdog reset [SWDT_RST internal signal]
Processor 0 reset [AWDT0_RST internal signal]
Processor 1 reset [AWDT1_RST internal signal]
System Software reset (slcr.PSS_RST_CTRL [SOFT_RST] bit)
Debug System reset [DBG_RST]
System reset [PS_SRST_B pin]
Power-on reset [PS_POR_B pin]

RST_REASON and RST_REASON_CLR Registers:

Useful for engineering samples only (not production devices). For production devices, use the REBOOT_STATUS register. The RST_REASON and RST_REASON_CLR registers no longer appear in the Zynq-7000 AP SoC Technical Reference Manual (TRM). These registers are documented here, in this Xilinx Answer, for engineering samples (Z-7020 GES and Z-7045 GES devices).

All silicon versions:

RST_REASON is read-only by software (user and BootROM). The register contains 7 bits corresponding to the seven possible reset sources. When a reset is detected by the hardware, a bit is set by the hardware. The register accumulates each reset reason so multiple bits might be set. The register is cleared by writing a 1 to the RST_REASON_CLR [0] register bit.
Note: These bits persist through all non-POR resets. When a POR reset occurs, only the POR bit will be set = 1.

Silicon 1.0 and 2.0:
In order for user code to determine the cause of the most recent reset, the user code is expected to clear the RST_REASON register after reading the reason of the reset so that next time a reset occurs, only one bit will be set.

Silicon 3.0:
These registers are de-featured for the user and the BootROM code is modified to manage these registers.  The user code does not need to (and should not access) the RST_REASON and RST_REASON_CLR registers.

REBOOT_STATUS Register:

All silicon versions:
This register contains 32 Read/Write bits that persist through all non-POR resets. The register bits can be written by the hardware, the BootROM or user code depending on the system state and silicon revision.
Bits [15:0]: When the boot process fails, the BootROM writes an error code into the [15:0] bits.

Note: the error codes for silicon 3.x are not the same used in silicon 1.0/2.0. The error codes for 1.0/2.0 are described in (Xilinx Answer 55082). The error codes for production silicon are described in the TRM.

Silicon 1.0 and 2.0:
Bits [31:16]: Not assigned or written by the BootROM or hardware.

Silicon 3.0:
Bits [31:24]: Not assigned or written by the BootROM or hardware.
Bits [23]: reserved.
Bits [22:16]: In order for user code to determine the cause of the most recent reset, the user code is expected to clear these bits after reading them so that next time a reset occurs, only one bit will be set.

 

Register Bits GES Z-7020 and GES Z-7045 Devices Production Devices

  

slcr.REBOOT_STATUS

0xF800_0258

31:24

 

General Purpose 32-bit R/W field
that persists through all resets except a POR reset.

Not assigned or written by the BootROM or hardware.

General Purpose 8-bit R/W field that persists except through all resets except a POR reset.
Not assigned or written by the BootROM or hardware.

23 reserved
22 Power-On Reset (POR), PS_POR_B signal
21 System Reset (SRST_B), SRST_B signal
20 Debug Reset (DBG_RST)
19 SLC soft Reset (SLC_RST)
18 CPU 1 Watchdog Reset (AWDT1_RST)
17 CPU 0 Watchdog Reset (AWDT0_RST)
16 System Watchdog Reset (SWDT_RST)
15:0 BootROM Error Code

 

slcr.RST_REASON

0xF800_0250

31:7 reserved

De-featured Register

6 Power-On Reset (POR), PS_POR_B signal
5 Debug Reset (DBG_RST)
4 System Reset (SRST_B), SRST_B signal
3 CPU 1 Watchdog Reset (AWDT1_RST)
2 CPU 0 Watchdog Reset (AWDT0_RST)
1 System Watchdog Reset (SWDT_RST)
0 BootROM Error Code

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 52030
Date Created 09/25/2012
Last Updated 06/03/2013
Status Active
Type Design Advisory
Devices
  • Zynq-7000
  • XA Zynq-7000
  • Zynq-7000Q