The problem requires the following conditions to occur:
With the above conditions, an internal "Data Side drain request" signal might remain sticky, causing the ISB to wait for the Data Side to be empty, which never happens because the last read or write operation waits for the ISB to complete.
|Impact:||Minor. The issue can lead to a deadlock; however, it can be prevented through a work-around.|
|Work-around:||A simple work-around for this erratum is to add a DSB at the beginning of the abort exception handler.|
|Configurations Affected:||Systems that use the CPUs.|
|Device Revision(s) Affected:||All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences.|
05/16/2013 - Initial release