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AR# 52033

Zynq-7000 AP SoC, APU - Speculative instruction fetches with MMU disabled might not comply with architectural requirements


The CPU usually operates with both the MMU and branch prediction enabled. If the processor operates in this condition for any significant amount of time, the BTAC (branch target address cache) will contain branch predictions. If the MMU is then disabled, but branch prediction remains enabled, these stale BTAC entries can cause the processor to make speculative instruction fetches to read-sensitive locations. This violates the ARMv7 architectural rules regarding speculative fetches documented in the ARM Architecture Reference Manual.


Minor. The CPU is mostly used with the MMU enabled. The issue can also be prevented through a simple work-around listed in the next section.
Invalidate all entries in the BTAC, by executing a BPIALL (invalidate entire branch prediction array) operation followed by a DSB, before disabling the MMU.
Another possible workaround is to disable branch prediction when disabling the MMU, and keep branch prediction disabled until the MMU is re-enabled.
Configurations Affected:
 Systems that use the CPUs.
Device Revision(s) Affected: All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences Answer Record.

Revision History
March 2013 new.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 52033
Date Created 09/25/2012
Last Updated 05/16/2013
Status Active
Type Design Advisory
  • XA Zynq-7000
  • Zynq-7000
  • Zynq-7000Q