This answer record highlights the important requirements and known issues for the Virtex-7 FPGA Initial Engineering Sample (IES) and General Engineering Sample (GES) program related to software and IP. These items are specifically relevant to designs targeting the Virtex-7 1140T IES and GES FPGA devices. Additional silicon limitations might exist, so reference the Initial ES errata that accompanies the devices.
This answer record is updated frequently as new information becomes available regarding known issues, patches, IP support, and more. Please check back often for the most current information.
Software Known Issues
All 7 series IP cores are listed as Pre-Production in the CORE Generator "Status" field. Support of Pre-Production cores on Initial ES FPGA devices is dependent on Xilinx hardware validation, which is ongoing throughout the ES period. IP that has been hardware validated is still subject to change as verification and characterization work continues. Consult the IP Known Issues Answer Records below for the most recent information.
IP Known Issues
Other Important Items
03/06/2013 - Removed GTX DA and update to Vivado version
11/19/2012 - Updates
05/02/2012 - Initial release