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How do I implement Vivado HLS generated RTL files with Synplify, XST, Vivado, or other RTL Synthesis tool?
Copy all of the RTL filed in the /verilog or /vhdl folder from the /<project>/solution/impl/ directory. In addtion, any .ngc or .xco files should also be copied to the source folder for the RTL synthesis tool.
AR# 52100 | |
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Date | 09/28/2012 |
Status | Active |
Type | Solution Center |
Tools |
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