Version Found: MIG v1.7
Version Resolved: See (Xilinx Answer 45195)
NOTE: THIS ANSWER RECORD AND INCLUDED PATCH HAS BEEN REPLACED BY (Xilinx Answer 53420). PLEASE VISIT THIS ANSWER RECORD.
The MIG 7 Series DDR3/DDR2 design fails during the final stage of calibration, PRBS Read Leveling, when targeting a 2:1 controller.
This is due to an error in the RTL code for 2:1 operation. The work-around is detailed below.
The debug signals do not include error flags for PRBS Read Leveling. To determine if calibration failed during PRBS read leveling, check that dbg_rdlvl_done=1 and init_calib_complete=0. This will signify the stage before PRBS Read Leveling, Read Leveling Stage 1, completed successfully. Because PRBS calibration is the final stage, you can know the failure occurred during this final stage.
To work around thisRTL error, perform the following:
1. Open the user_design/rtl/phy/mig_7series_v1_7_ddr_phy_prbs_rdlvl.v module and locate line 414:
end else if (mux_rd_valid_r) begin //Needs to be updated to rd_valid_r1
compare_err_r0 <= #TCQ (mux_rd_rise0_r2 !== compare_data_r0);
compare_err_f0 <= #TCQ (mux_rd_fall0_r2 !== compare_data_f0);
compare_err_r1 <= #TCQ (mux_rd_rise1_r2 !== compare_data_r1);
compare_err_f1 <= #TCQ (mux_rd_fall1_r2 !== compare_data_f1);
compare_err <= #TCQ (compare_err_r0 | compare_err_f0 |
compare_err_r1 | compare_err_f1);
2. Replace mux_rd_valid_r on line 414 with rd_valid_r1.
3. Implement the design again. PRBS calibration should now pass successfully.
10/16/12 - Initial release
12/11/12 - Minor update