Version Found: MIG 7 Series v1.7
Version Resolved: See (Xilinx Answer 45195)
Table 1-13: Traffic Generator Signal Descriptions in the 7 Series FPGAs Memory Interface Solutions Guide states that the vio_data_mode_value[3:0] can be set to "0xF: PHY_CALIB pattern."
This pattern should result in the write calibration data pattern of 0xFF, 00, AA, 55, 55, AA, 99, 66.
However, the "0xF" setting results in the Address as Data pattern (0x2) mode only generating READ commands at address zero.