UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 52135

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.4 - 7 Series - 500 ns delay needed for GTTXRESET and GTRXRESET

Description

The 7 Series GTX/GTH Transceivers require a 500 ns delay before asserting GTTXRESET and GTRXRESET after configuration. 

This reset requirement is described in the GTX/GTH Transceiver Users Guide and in (Xilinx Answer 43482).

This delay was correctly applied in the previous v11.3 Ethernet 1000BASE-X PCS/PMA or SGMII core.

Solution

The delay can be added by making the following change in the example_design/transceiver/core_name_transciever.v/vhd file.

If using Verilog change:

   assign gt_reset_rx = !cplllock || (rxreset_int & resetdone_rx);
   assign gt_reset_tx = !cplllock || (txreset_int & resetdone_tx);

      
To:

   assign gt_reset_rx = rxreset_int & resetdone_rx;
   assign gt_reset_tx = txreset_int & resetdone_tx;


If using VHDL change:

   gt_reset_rx <= not cplllock or (rxreset_int and resetdone_rx);
   gt_reset_tx <= not cplllock or (txreset_int and resetdone_tx);


To:

   gt_reset_rx <= (rxreset_int and resetdone_rx);
   gt_reset_tx <= (txreset_int and resetdone_tx);



AR# 52135
Date Created 10/01/2012
Last Updated 09/08/2014
Status Active
Type General Article
IP
  • Ethernet 1000BASE-X PCS/PMA or SGMII