Version Found: MIG Virtex-6 and Spartan-6 v3.92
Version Resolved: Not Resolved
The MIG Virtex-6 v3.92 DDR3 VHDL example design might fail timing on the following constraint:
Please use the Verilog generated design as a work-around as this issue only affects MIG Virtex-6 FPGA DDR3 VHDL designs.
10/16/2012 - Initial release