What files are required to initialize a Virtex block RAM in HDL behavioral simulation?
COREGEN v1.5 and v1.4:
For both Verilog and VHDL behavioral simulation of Virtex
Block RAM generated by the Xilinx CORE Generator, the
behavioral simulation netlist (design.v or design.vhd) is
required, PLUS an additional design.MIF (Memory Initialization
File), which contains the initialization data for the RAM.
The MIF file is an ASCII text file that is referenced by
the .v (Verilog) or .vhd (VHDL) netlist. It must be present
in the same directory as the HDL behavioral simulation netlist
when you run your simulation.
- In a Verilog behavioral netlist for a block RAM, the MIF is
read in using a $readmemb directive:
$readmemb ("<design>.mif", ram_temp);
- In a VHDL behavioral netlist for a block RAM, the MIF is read
in using a FILE record:
FILE meminitfile: TEXT IS IN "<design>.mif"
All of the above is generated automatically by COREGEN when the
"EDIF Netlist" output option is selected in the COREGEN Output