UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 52183

ISE / 7 Series - ODELAY component functional delay modeling

Description

In ISE simulation for 7 series ODELAY component, tap delay in FIXED mode is not correctly shown.

Solution

In 7 series Devices, the ODELAY component has a number of parts to the delay that are modeled in functional simulation.
 
The first part of the delay is the insertion delay which is a fixed delay of the ODELAY component.

This delay is fixed regardless of the tap setting. The delay of this portion is 600ps in the 7 series devices.
 
The second part of the delay is a per-tap delay which models the total delay through the component in FIXED mode.

This delay is a linear  function of the TAP setting multiplied by the per-tap-delay.
 
Note: In the ISE software up to and including 14.3 the ODELAY per-tap delay component is not modeled correctly, and only the insertion delay is seen.

This issue is fixed in the 14.4 release.
AR# 52183
Date Created 10/02/2012
Last Updated 07/29/2014
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • ISE Design Suite - 14.1
  • ISE Design Suite - 14.2
  • ISE Design Suite - 14.3