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AR# 52193

Design Advisory for 7 Series BPI Multiboot - When fallback occurs, flash access is always in BPI Asynchronous Mode


7 serieshas BPI synchronousmode support. Synchronous mode utilizes the CCLK to clock data from the flash and can be run at a higher data rate than asynchronous reads.BPI synchronous mode is available for first time and Multiboot configuration. Fallback configuration will always default toBPIasynchronousmode even if the first time or Multiboot configuration uses synchronous mode.


This is a critical consideration for applications relying on Fallback for "Safe update" methods. The Bitgen -g confgrate setting to set the configuration clock speed on the "Golden" bistream needs to be considered. To determine the maximum frequency refer to the "Determining the Maximum Configuration Clock Frequency" section in the "7 series Configuration User Guide". For customers using EMCCLK as a configuration clock source you are unlikely to have a clock frequency slow enough for asynchronous BPI mode.

There are some potential work-arounds for this issue:

(1) Use RS pins to configure multiboot image in SYNC mode at higher speeds and keep Golden image as ASYNC operating at a lower speed

  • This is a solution for systems that require a fast configuration on first boot

(2) Set Configrate or EMCCLK frequency at a rate that will no violate BPI flash timing specifications as set out in UG470

  • This solution allows a consistent approach between the two images, but reduces configuration speed

If you require further assistance on this issue, please open a case with Xilinx Technical Support -


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
42946 Design Advisory Master Answer Record for Kintex-7 FPGA N/A N/A
51456 Design Advisory Master Answer Record for Artix-7 FPGA N/A N/A
AR# 52193
Date Created 10/25/2012
Last Updated 01/28/2013
Status Active
Type General Article
  • Kintex-7
  • ISE