This is a critical consideration for applications relying on Fallback for "Safe update" methods. The Bitgen -g confgrate setting to set the configuration clock speed on the "Golden" bistream needs to be considered. To determine the maximum frequency refer to the "Determining the Maximum Configuration Clock Frequency" section in the "7 series Configuration User Guide". For customers using EMCCLK as a configuration clock source you are unlikely to have a clock frequency slow enough for asynchronous BPI mode.
There are some potential work-arounds for this issue:
(1) Use RS pins to configure multiboot image in SYNC mode at higher speeds and keep Golden image as ASYNC operating at a lower speed
(2) Set Configrate or EMCCLK frequency at a rate that will no violate BPI flash timing specifications as set out in UG470
If you require further assistance on this issue, please open a case with Xilinx Technical Support -