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AR# 52199

LogiCORE IP Floating Point Operator (FPO) v6.1 - Why do I get a Synthesis CRITICALWARNING: [EDIF 20-96] when synthesizing the Floating Point Operators with Vivado Synthesis in the 2012.2 tool?

Description

Why do I get a Synthesis CRITICALWARNING: [EDIF 20-96] warning when synthesizing the Floating Point Operators with Vivado Synthesis in the 2012.2 tool?

CRITICALWARNING: [EDIF 20-96] Could not resolve non-primitive black box cell 'delay_line__parameterized11_143' defined in file '' instantiated as 'use_DSP48E.appDSP48E[0].bppDSP48E[0].need_output_dela

Solution

This is a known issue in Vivado Synthesis that is resolved in the Vivado 2012.3 tool.

You can work around this by using XST Synthesis (if you are using the Vivado 2012.2 tool).

For a detailed list of LogiCORE IP Floating Point Operator Release Notes and Known Issues, see (Xilinx Answer 29598).

AR# 52199
Date Created 10/03/2012
Last Updated 10/09/2013
Status Active
Type General Article
IP
  • Floating Point Operators