"> AR# 52250: 14.2 TRCE/Timing Analyzer - Why is the clock of the write process used in the Timing report in the read path of Distributed RAM if this is asynchronous?

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AR# 52250

14.2 TRCE/Timing Analyzer - Why is the clock of the write process used in the Timing report in the read path of Distributed RAM if this is asynchronous?

Description

In the Timing Analysis report, Ihave the"Tshcko" for the calculations of the read pathin a Distributed RAM.
Why do I have this delay value if it is related to the writing process?


Solution

In UG364 there is an explanation of the distributed RAM read/write process on page 38.
This distributed RAM can only be implemented into SLICEM.



As we can see, in the asynchronous reading process the Time delay for the reset processis,"Tilo" (propagation delay from the inputs through the look-up table to the output).
However, in the Timing Analysis the value reported is "Tshcko" (Time after the CLK of a write operation the data written is stable on the outputs).

This is because the tools work with the worstcase scenario for the Timing Analysis.
In this situation the longer time delay happens when a Writing process is done in the distributed RAM, and then a read process from the same memory position is carried out.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
39606 Distributed RAM Memory- How avoid memory collisions N/A N/A
39618 Design Assistant for XST - Inference concerns with Distributed RAM N/A N/A
AR# 52250
Date Created 10/05/2012
Last Updated 10/11/2012
Status Active
Type General Article
Devices
  • Virtex-6
Tools
  • ISE Design Suite
  • ISE Design Suite - 14.1
  • ISE Design Suite - 14.2