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AR# 52261

Known Issues and Work-arounds with 7 Series GTZ Transceiver Wizard in Vivado 2012.3


This answer record covers known issues with v2.3 of the 7 series FPGAs Transceivers Wizard targeting GTZ Transceivers in Vivado 2012.3 Design Suite.


Port and Attribute Changes:

  1. Port CFGDEBUGMODEB[2:0] in the octal wrapper (gtwizard_v2_3_octal0.v) should be tied High instead of Low (tied_to_vcc_vec_i[2:0] instead of tied_to_ground_vec_i[2:0])
  2. Port CFGFORCESEUERRB[1:0] in the octal wrapper (gtwizard_v2_3_octal0.v) should be tied High instead of Low (tied_to_vcc_vec_i[1:0] instead of tied_to_ground_vec_i[1:0])
  3. Port CFGREADBACKB in the octal wrapper (gtwizard_v2_3_octal0.v) should be tied High instead of Low (tied_to_vcc_vec_i instead of tied_to_ground_vec_i)
  4. For RAW mode designs, modify line number 392 of the file gtwizard_v2_3_gt_frame_check.v from:
          if (rx_data_aligned != bram_data_r)
          if (rx_data_aligned != bram_data_c)

  5. If the wizard generated design is modified to drive the DRPCLK and CFGCLKs, the BUFGs driving the DRPCLK0, CFGCLK and DRPCLK1 should be locked to BUFG_X0Y14, BUFG_X0Y15, BUFG_X0Y17 respectively.
    For example, add this line to the xdc file: 

    set_property LOC BUFGCTRL_X0Y14 [get_cells -hier -filter {name =~*drpclk0_buf}]

  6. Port B2M_RSVDIN in the beachfront (gtwizard_v2_3_beachfront.v) should be driven to 15'b111100000000000 instead of 15'h0000
  7. Attribute SBUS_CLK_DIV_NON_2N_RESET_VAL in the octal wrapper (gtwizard_v2_3_octal0.v) should be driven to 12'hFFF instead of 12'h000

CTLE tuning:

In addition to the port and attribute changes to the 2012.3 Wizard mentioned above, the CTLE needs to be tuned. For details on CTLE tuning procedure, refer to the 7 Series FPGAs GTZ Transceiver User Guide (UG478 v2.0 or later).

Note: The "Version Found" column lists the version the problem was first discovered. The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions. This is an issue with latency of the core.

AR# 52261
Date Created 11/08/2012
Last Updated 07/30/2013
Status Active
Type Known Issues
  • Virtex-7 HT
  • Vivado Design Suite - 2012.3
  • 7 Series FPGAs Transceivers Wizard