UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 52288

MIG 7 Series DDR2/DDR3 - Byte lane architecture does not support x4 DIMMs

Description

The 7 Series MIG design cannot support x4 DIMMs because of the byte lane architecture.

Solution

7 series devices have four byte groups in a bank, and only a single DQS strobe pair available for each byte group. MIG only supports interfaces that span three contiguous vertical banks, and using 16 or 18 DQS strobes (16/18 byte groups) would require more than three contiguous banks. For this reason, MIG does not support x4 DIMMs with 7 series devices.

AR# 52288
Date Created 10/08/2012
Last Updated 10/18/2012
Status Active
Type General Article
Devices
  • Kintex-7
  • Virtex-7
  • Artix-7
  • Zynq-7000
IP
  • MIG 7 Series