Why is a -2 or -3 part required to support 5.4 Gb/s in 7 series FPGAs?
The Product Guide (PG064) says: "For a 5.4 Gb/s link rate, a high performance 7 series FPGA is required with speed grade -2 or -3."
This is due to limitations on the speed of the GTX Transceiver User Clock when the data path of 16-bits is selected.
More information can be found in the GTP, GTX / GTX section of the data sheets for the respective 7 series devices:
For a detailed list of LogiCORE IP DisplayPort Release Notes and Known Issues, see (Xilinx Answer 33258).