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AR# 52299

LogiCORE IP DisplayPort v3.2 - Why is a -2 or -3 part required to support 5.4 Gb/s in 7 Series FPGAs?


Why is a -2 or -3 part required to support 5.4 Gb/s in 7 series FPGAs?

The Product Guide (PG064) says: "For a 5.4 Gb/s link rate, a high performance 7 series FPGA is required with speed grade -2 or -3."


This is due to limitations on the speed of the GTX Transceiver User Clock when the data path of 16-bits is selected.

More information can be found in the GTP, GTX / GTX section of the data sheets for the respective 7 series devices:

For a detailed list of LogiCORE IP DisplayPort Release Notes and Known Issues, see (Xilinx Answer 33258).

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AR# 52299
Date Created 10/09/2012
Last Updated 10/31/2013
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • DisplayPort