When importing functions in System Verilog Interfaces, ports get connected incorrectly.
Does Vivado Synthesis support import methods (SystemVerilog functions and tasks) from System Verilog Interface?
Today, Vivado Synthesis does not support import methods (SystemVerilog functions and tasks) from System Verilog Interface.
Here is an example of an import method that is not supported:
// function define within an Interface
function example_test (.....);
// Import method
modport test (input a, b, import function example_test( ));