Starting in version 2012.4, Vivado Synthesis does support non-constant (dynamic) range expression.
Prior to 2012.4, Vivado Synthesis did not support non-constant (dynamic) range expression and failed with message saying "range expression could not be resolved to a constant".
The following example depicts this issue in prior 2012.4 Vivado Synthesis and works in 2012.4 Vivado Synthesis,
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test is port (
in1, in2 : in std_logic_vector(3 downto 0);
clk : in std_logic;
in3 : in std_logic_vector(15 downto 0);
out1 : out std_logic_vector(15 downto 0));
end test;
architecture beh of test is
signal high, low : integer;
begin
high <= conv_integer(in2);
low <= conv_integer(in1);
process(clk)
begin
if clk'event and clk='1' then
out1(high downto low) <= in3(high downto low);
end if;
end process;
end beh;
Prior to 2012.4, this type of coding stylewas not supported in Vivado Synthesis. In the example above, what is being assigned to out1 from in3 is not static and is based on the inputs to the design. The problem is that there is an assignment to, or a read from, a vector where the high and low ranges do not evaluate to a constant. As a result, the recommended option to get around this problem was to have static values rather than dynamic values for ranges.